UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 195

• Manufacturer Part Number: UPD784026
• Description: 16/8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

5.11 CAUTIONS
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) If the output levels of a port in which control outputs and port outputs are mixed in a single port are checked with the
All port pins become high-impedance after RESET signal input (internal pull-up resistors are disconnected from the
pins).
If there is a problem with pins becoming high-impedance during RESET input, this should be handled with external
circuitry.
Bit 7 of the pull-up resistor option register (PUO) that sets the internal pull-up resistor connection is fixed at 0, but if “1”
is written to bit 7 of the PUO in the in-circuit emulator, “1” will be read.
Output latch contents are not initialized by RESET input. When a port is used as an output port, the output latch must
be initialized without fail before turning on the output buffer. If the output latch is not initialized before turning on the output
buffer, unexpected data will be output to the output port.
Similarly, for pins used as control pins, internal peripheral hardware initialization must be performed before performing
the control pin specification.
As P22 to P26 are not pulled up immediately after a reset, an interrupt request flag may be set depending on the function
of the dual-function pins (INTP1 to INTP5). Therefore, the interrupt request flags should be cleared after specifying pull-
up in the initialization routine.
When P40 to P47 and P50 to P57 are used as the address/data bus and address bus respectively in the PD784026,
bits PUO4 and PUO5 of the pull-up resistor option register (PUO) must be set to “0” so that internal pull-up resistor
connection is not performed.
Also, since P40 to P47 and P50 to P57 are used as the address/data bus and address bus respectively in the
In the PD784021, P60 to P63 are in the high-impedance state during RESET input/output, but output low level after
RESET release. Therefore, external circuitry should be designed so that output of a low-level signal as the initial state
is no problem.
A voltage outside the range AV
See 14.5 CAUTIONS IN CHAPTER 14 A/D CONVERTER for details.
A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. Therefore, if a bit
manipulation instruction is used on a port with a mixture of input and output pins or port mode and control mode, the
contents of the output latch of pins specified as inputs or pins specified as in control mode will be undefined (excluding
bits manipulated with a SET1 or CLR1 instruction, etc.). Particular care is required when there are bits which are
switched between input and output.
Caution is also required when manipulating the port with other 8-bit operation instructions.
If each port is set to input mode, a comparison of the pin status with the output latch contents (or control output level)
using the CHKL or CHKLA instruction will always show a match whether the individual pins of the port are port pins or
control pins. Therefore, executing these instructions on a port set to input mode is actually ineffective.
CHKL or CHKLA instruction, the input/output mode of control output pins should be set to input mode before executing
these instructions (as the output levels of control outputs vary asynchronously, the output level cannot be checked with
the CHKL or CHKLA instruction).
PD784021, bits PUO4 and PUO5 must be set to “0” so that internal pull-up resistor connection is not performed.
SS
to AV
CHAPTER 5 PORT FUNCTIONS
REF
must not be applied to pins for which P70 to P77 are used as ANI0 to ANI7.
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