UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 565

• Manufacturer Part Number: UPD784026
• Description: 16/8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

Figure 20-13 Examples of Processing When Another Interrupt Request is Generated During Interrupt Processing (3/3)
* 1. Low default priority
Remarks 1. “a” to “z” in the figure are arbitrary names used to differentiate between the interrupt requests and macro
2. High default priority
Interrupt Request x
Interrupt Request u
Interrupt Request q
(Level 1)
(Level 0)
Level 3)
2. High/low default priorities in the figure indicate the relative priority levels of the two interrupt requests.
service requests.
Main routine
EI
Interrupt
Request y*
(Level 2)
Request z*
Request w
Interrupt
Request v
(Level 0)
Request r
Interrupt
(Level 2)
(Level 3)
Interrupt
(Level 2)
Interrupt
2
1
EI
EI
q Processing
u Processing
v Processing
x Processing
z Processing
y Processing
Request s
Interrupt
(Level 1)
CHAPTER 20 INTERRUPT FUNCTIONS
EI
r Processing
w Macro Service
Request t
Interrupt
(Level 0)
EI
s Processing
EI
t Processing
Multiple acknowledgment of levels 3 to 0. If
the PRSL bit of the IMC register is set (1),
only macro service requests and non-
maskable interrupts generate nesting
beyond this.
If the PRSL bit of the IMC register is
cleared (0), level 3 interrupts can also be
nested during level 3 interrupt processing
(see Figure 20-15).
Even though the interrupt enabled state is
set during processing of level 0 interrupt
request u, the interrupt request is not
acknowledged but held pending even
though its priority is 0. However, the macro
service request is acknowledged and
processed irrespective of its level and even
though there is a pending interrupt with a
higher priority level.
Pending interrupt requests y and z are
acknowledged after processing of interrupt
request x. As interrupt requests y and z
have the same priority level, interrupt
request z which has the higher default
priority is acknowledged first, irrespective
of the order in which the interrupt requests
were generated.
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