UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 485

• Manufacturer Part Number: UPD784026
• Description: 16/8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

17.4.3 Operation When Reception Only Is Enabled
receive operation starts when the CRXE changes from “0” to “1”, or when a read from shift register (SIO) is performed.
(1) When the internal clock is selected as the serial clock
(2) When an external clock is selected as the serial clock
A receive operation is performed when the CRXE bit of the clocked serial interface mode register (CSIM) is set (1). The
When reception starts, the serial clock is output from the SCK0 pin and the SI0 pin data is fetched in sequence into
shift register (SIO) in synchronization with the rise of the serial clock.
There is a delay of up to one SCK0 clock cycle between the start of reception and the first fall of SCK0.
If reception is disabled during the receive operation (by clearing (0) the CRXE bit), SCK0 clock output is stopped and
the receive operation is discontinued on the next rise of SCK0. In this case an interrupt request (INTCSI) is not
generated, and the contents of the SIO register will be undefined.
When reception starts, the SI0 pin data is fetched into shift register (SIO) in synchronization with the rise of the serial
clock input to the SCK0 pin after the start of reception. If reception has not started, shift operations are not performed
even if the serial clock is input to the SCK0 pin.
If reception is disabled during the receive operation (by clearing (0) the CRXE bit), the receive operation is discontinued
and subsequent SCK0 input is ignored. In this case an interrupt request (INTCSI) is not generated.
CHAPTER 17 CLOCKED SERIAL INTERFACE
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