UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 486

• Manufacturer Part Number: UPD784026
• Description: 16/8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

17.4.4 Operation When Transmission/Reception Is Enabled
and receive operation can be performed simultaneously (transmit/receive operation). The transmit/receive operation is
started when the CRXE bit is changed from “0” to “1”, or by performing a write to shift register (SIO).
a possibility that the transmit/receive operation will start immediately, and undefined data will be output. The first transmit
data should therefore be written to SIO beforehand when both transmission and reception are disabled (when the CTXE
bit and CRXE bit are both cleared (0)), before enabling transmission/reception.
(1) When the internal clock is selected as the serial clock
(2) When an external clock is selected as the serial clock
446
When the CTXE bit and CRXE bit of the clocked serial interface mode register (CSIM) are both set (1), a transmit operation
When a transmit operation is started for the first time, the CRXE bit always changes from “0” to “1”, and there is thus
When transmission/reception is disabled (CTXE = CRXE = 0), the SO0 pin is in the output high impedance state.
When transmission/reception starts, the serial clock is output from the SCK0 pin, data is output in sequence from shift
register (SIO) to the SO0 pin in synchronization with the fall of the serial clock, and SI0 pin data is shifted in order into
SIO in synchronization with the rise of the serial clock.
There is a delay of up to one SCK0 clock cycle between the start of transmission and the first fall of SCK0.
If either transmission or reception is disabled during the transmit/receive operation, only the disabled operation is
discontinued. If transmission only is disabled, the SO0 pin becomes output high impedance. If reception only is
disabled, the contents of the SIO register will be undefined.
If transmission and reception are disabled simultaneously, SCK0 clock output is stopped and the transmit and receive
operations are discontinued on the next rise of SCK0. When transmission and reception are disabled simultaneously,
the contents of SIO are undefined, an interrupt request (INTCSI) is not generated, and the SO0 pin becomes output
high impedance.
When transmission/reception starts, data is output in sequence from shift register (SIO) to the SO0 pin in synchroni-
zation with the fall of the serial clock input to the SCK0 pin after the start of transmission/reception, and SI0 pin data
is shifted in order into SIO in synchronization with the rise of the serial clock. If transmission/reception has not started,
shift operations are not performed and the SO0 pin output level does not change even if the serial clock is input to
the SCK0 pin.
If either transmission or reception is disabled during the transmit/receive operation, only the disabled operation is
discontinued. If transmission only is disabled, the SO0 pin becomes output high impedance. If reception only is
disabled, the contents of the SIO register will be undefined.
If transmission and reception are disabled simultaneously, the transmit and receive operations are discontinued and
subsequent SCK0 input is ignored. When transmission and reception are disabled simultaneously, the contents of SIO
are undefined, an interrupt request (INTCSI) is not generated, and the SO0 pin becomes output high impedance.
CHAPTER 17 CLOCKED SERIAL INTERFACE