UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 640
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UPD784026
Manufacturer Part Number
UPD784026
Description
16/8-bit Single-chip Microcontrollers
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD784026.pdf
(759 pages)
- Current page: 640 of 759
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(2) Refresh area specification register (RFA)
21.3.2 Operations
(1) Pulse refresh operation
600
(n= 0 to 7)
RFAn
Table 21-1 System Clock Frequency and Refresh Pulse Output Cycle When Pseudo-Static RAM is Used
The RFA is an 8-bit register that specifies the areas on which refresh operations can be performed at the same time
as memory access operations.
The RFA register can be read or written to with an 8-bit manipulation instruction and bit manipulation instruction. RFA
format is shown in Figure 21-16.
RESET input clears the RFA register to 00H.
To support the pulse refresh cycles of pseudo-static RAM, refresh pulses are output from the REFRQ pin in
synchronization with bus cycles.
The system clock frequency and bits 1 and 0 (RFT1/RFT0) of the refresh mode register (RFM) are adjusted so that
512 or more refresh pulses are generated in an 8ms period.
These pulse refresh operations are performed so that they do not overlap external memory access operations. During
a refresh cycle, an external memory access cycle is held pending (ASTB, RD, WR, etc. are inactive), and during an
external memory access cycle, a refresh cycle is held pending.
If there is no overlapping with an external memory access operation, the refresh cycle is performed without affecting
CPU instruction execution.
Refresh
Specification
Area
0
1
RFA
System Clock Frequency
080000H to
Refreshing performed at same time as memory access operations in corresponding block
Refreshing performed exclusively from memory access operations in corresponding block
0FFFFFH
4.096 < f
2.048 < f
8.192 < f
RFA7
7
Figure 21-16 Refresh Area Specification Register (RFA) Format
(f
CLK
) MHz
CLK
CLK
CLK
040000H to
07FFFFH
RFA6
CHAPTER 21 LOCAL BUS INTERFACE FUNCTION
6
8.192
4.096
12.5
020000H to
03FFFFH
RFA5
5
Refresh Pulse Output Cycle Specification
010000H to
01FFFFH
RFA4
4
00C000H to
00FFFFH
128/f
64/f
32/f
RFA3
3
CLK
CLK
CLK
008000H to
00BFFFH
2
RFA2
004000H to
007FFFH
1
RFA1
RFT1
1
0
0
000000H to
003FFFH
0
RFA0
RFT0
0
1
0
0FFCDH
Address On Reset R/W
00H
R/W
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