UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 102
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UPD784026
Manufacturer Part Number
UPD784026
Description
16/8-bit Single-chip Microcontrollers
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD784026.pdf
(759 pages)
- Current page: 102 of 759
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* When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, 0F0000H should be
Caution R4, R5, R6, R7, RP2 and RP3 can be used as the X, A, C, B, AX and BC registers respectively by setting
Remark When the register bank is changed, and it is necessary to return to the original register bank, an SEL RBn
added to the address values shown above.
FEFFH*
FE80H*
the RSS bit of the PSW to 1, but this function should only be used when using a 78K/III series program.
instruction should be executed after saving the PSW to the stack with a PUSH PSW instruction. When returning
to the original register bank, if the stack location does not change the POP PSW instruction should be used.
When the register bank is changed by a vectored interrupt service program, etc., the PSW is automatically saved
to the stack when an interrupt is acknowledged and restored by an RETI or RETB instruction, so that, if only one
register bank is used in the interrupt service routine, only an SEL RBn instruction needs be executed, and
execution of a PUSH PSW and POP PSW instruction is not necessary.
Example When register bank 2 is specified
RBNK0
RBNK1
RBNK2
RBNK3
RBNK4
RBNK5
RBNK6
RBNK7
PUSH PSW
SEL RB2
POP PSW
Figure 3-13 General-Purpose Register Addresses
CHAPTER 3 CPU ARCHITECTURE
Operations in register bank 2
Operations in original register bank
7
H(R15)
D(R13)
B(R3)
A(R1)
R11
R9
R7
R5
8-Bit Processing
(9H)
(7H)
(5H)
(BH)
(3H)
(1H)
(DH)
(FH)
0
7
E(R12)
L(R14)
C(R2)
X(R0)
R10
R8
R6
R4
(8H)
(6H)
(4H)
(AH)
(0H)
(2H)
(EH)
(CH)
0
15
16-Bit Processing
DE(RP6)
UP(RP5)
AX(RP0)
HL(RP7)
VP(RP4)
BC(RP1)
RP3
RP2
(6H)
(4H)
(EH)
(CH)
(0 H)
(AH)
(8H)
(2H)
0
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