UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 531

• Manufacturer Part Number: UPD784026
• Description: 16/8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

19.4 PIN EDGE DETECTION FOR PINS P22 TO P24
P21 pin, f
in succession (if it is the same only 2 or fewer times in succession), it is eliminated as noise. Therefore, the level must
be maintained for at least 4 f
as a valid edge.
Edge detection for pins P22 to P24 is performed after digital noise elimination by means of clock sampling. Unlike the
In digital noise elimination, input is sampled using the f
P22 to P24 Input Signal
Cautions 1. Since digital noise elimination is performed with the f
after Noise Elimination
P22 to P24 Input
CLK
Falling Edge
Rising Edge
is used as the sampling clock.
2. If the input pulse width is 3 to 4 f
3. If noise input to a pin is synchronized with the f
between input of an edge to the pin and the point at which the edge is actually detected.
Therefore, to ensure reliable operation, the level should be held for at least 4 clocks.
as noise. If there is a possibility of such noise being input, noise should be eliminated by adding
a filter to the input pins.
f
CLK
CLK
Digital noise elimination
with f
clock cycles (0.32 s: f
CLK
Figure 19-6 Edge Detection for Pins P22 to P24
clock
CHAPTER 19 EDGE DETECTION FUNCTION
CLK
CLK
clocks, it is uncertain whether a valid edge will be detected.
= 12.5 MHz, f
CLK
clock, and if the input level is not the same at least 4 times
CLK
clock in the PD784026, it may not be recognized
CLK
= 1/2 f
CLK
clock, there is a delay of 3 to 4 f
XX
, f
XX
= 25 MHz) in order to be recognized
CLK
clocks
491