UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 631
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UPD784026
Manufacturer Part Number
UPD784026
Description
16/8-bit Single-chip Microcontrollers
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD784026.pdf
(759 pages)
- Current page: 631 of 759
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21.2.3 Access Waits
= 12.5 MHz) per cycle.
number of cycles, or the external wait function controlled by a wait signal from outside.
is specified for each space by means of the programmable wait control registers (PWC1/PWC2). Waits are not inserted
in accesses to internal ROM or internal RAM using high-speed fetches. In accesses to internal SFRs, waits are inserted
at the necessary times regardless of this specification.
inserted also in internal ROM accesses in accordance with the PWC1 settings.
P66 pin operates as the WAIT signal input pin. After RESET input, the P66 pin operates as a general-purpose input/output
port.
Access waits are inserted in the RD or WR signal low-level period, and extend the low-level period by 1/f
There are two wait insertion methods, using either the programmable wait function that automatically inserts the preset
For wait cycle insertion control, the 1 M-byte memory space is divided into eight as shown in Figure 21-11, and control
If access operations are specified as being performed in the same number of cycles as for external ROM, waits are
If there is a space for which control by a wait signal from outside has been selected by means of the PWC1/PWC2, the
Bus timing in the case of access wait insertion is shown in Figures 21-12 to 21-14.
Cautions 1. The external wait function cannot be used when the bus hold function is used.
2. Do not set external wait for the internal ROM area. If external wait is set for the internal ROM area,
the CPU is deadlocked. This deadlock status can be cleared only by reset input.
CHAPTER 21 LOCAL BUS INTERFACE FUNCTION
CLK
(80 ns: f
591
CLK
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