UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 463

• Manufacturer Part Number: UPD784026
• Description: 16/8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

16.3.6 Operation When Transmission/Reception is Enabled
transmit operation and receive operation can be performed simultaneously (transmit/receive operation). The transmit/
receive operation is started when the CRXE1 bit is changed from “0” to “1”, or by performing a write to shift register (SIO1).
is thus a possibility that the transmit/receive operation will start immediately, and undefined data will be output. The first
transmit data should therefore be written to SIO1 beforehand when both transmission and reception are disabled (when
the CTXE1 bit and CRXE1 bit are both cleared (0)), before enabling transmission/reception.
(1) When the internal clock is selected as the serial clock
(2) When an external clock is selected as the serial clock
When the CTXE1 bit and CRXE1 bit of the clocked serial interface mode register (CSIM1) register are both set (1), a
When a transmit/receive operation is started for the first time, the CRXE1 bit always changes from “0” to “1”, and there
When transmission/reception is disabled (CTXE1 = CRXE1 = 0), the SO1 pin is in the output high level.
When transmission/reception starts, the serial clock is output from the SCK1 pin, data is output in sequence from shift
register (SIO1) to the (SO1) pin in synchronization with the fall of the serial clock, and SI1 pin data is shifted in order
into SIO1 in synchronization with the rise of the serial clock.
There is a delay of up to one SCK1 clock cycle between the start of transmission and the first fall of SCK1.
If either transmission or reception is disabled during the transmit/receive operation, only the disabled operation is
discontinued. If transmission only is disabled, the SO1 pin becomes output high level. If reception only is disabled,
the contents of the SIO1 will be undefined.
If transmission and reception are disabled simultaneously, SCK1 clock output is stopped and the transmit and receive
operations are discontinued on the next rise of SCK1. When transmission and reception are disabled simultaneously,
the contents of SIO1 are undefined, an interrupt request (INTCSI1) is not generated, and the SO1 pin becomes output
high level.
When transmission/reception starts, data is output in sequence from shift register (SIO1) to the SO1 pin in
synchronization with the fall of the serial clock input to the SCK1 pin after the start of transmission/reception, and SI1
pin data is shifted in order into SIO1 in synchronization with the rise of the serial clock. If transmission/reception has
not started, the SIO1 shift operations are not performed and the SO1 pin output level does not change even if the serial
clock is input to the SCK1 pin.
If either transmission or reception is disabled during the transmit/receive operation, only the disabled operation is
discontinued. If transmission only is disabled, the SO1 pin becomes output high level. If reception only is disabled,
the contents of the SIO1 will be undefined.
If transmission and reception are disabled simultaneously, the transmit and receive operations are disconti-nued and
subsequent SCK1 input is ignored. When transmission and reception are disabled simultaneously, the contents of SIO1
are undefined, an interrupt request (INTCSI1) is not generated, and the SO1 pin becomes output high level.
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
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