UPD784026 Renesas Electronics Corporation., UPD784026 Datasheet - Page 757

• Manufacturer Part Number: UPD784026
• Description: 16/8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

3rd edition
Edition
Change of 78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM
• Correction of Figure 3-1 PD784020 Memory Map
• Addition of caution on prohibiting external wait setting for internal ROM area
• Addition of note on reading timer register
• Addition of caution on reading timer register
• 8.5 EXTERNAL EVENT COUNTER FUNCTION
• 8.7.2 Toggle Output
• 8.7.3 PWM Output (3) Stopping PWM output
• Addition of caution on reading timer register
• Correction of timing of TM1 in Figure 9-10 Timing of External Event Count by Timer/
• 10.2 CONFIGURATION
• 10.5 EXTERNAL EVENT COUNTER FUNCTION
• 10.8.2 Toggle Output
• 10.8.3 PWM Output (3) Stopping PWM output
Addition of caution on reading timer register
Change of “If the STOP mode or IDLE mode is entered as the result of an inadvertent program
loop” to “If the STOP mode, HALT mode, or IDLE mode is entered as the result of an inadvertent
program loop” in <5> of (2) in 12.4.1 General Cautions on Use of Watchdog Timer
Low-speed conversion (f
Change from 240/f
• Addition of note on disabling reception completion interrupt in case of receive error and wait
• Addition of caution on selecting MSB/LSB first
Unification from CLO to CLKOUT pin
Addition of instructions to 20.9 WHEN INTERRUPT REQUESTS AND MACRO SERVICE
ARE TEMPORARILY HELD PENDING
Correction of timing of TM0 in Figure 8-10 Timer/Counter 0 External Event Count Timing
Change from “the output level at the time it was stopped is retained” to “the inactive level
(ALVn: n = 0, 1) is output” when timer/counter 0 is stopped by timer control register 0
Change from “the output level at the time it was stopped is retained” to “the active level is
output” when timer/counter 0 is stopped by timer control register 0
Counter 1
Addition of caution on reading timer register to (1) Timer register 2 (TM2/TM2W)
Deletion of “Also, the count value can be cleared by a match (CR21/CR21W)” from
description in (2) Compare register (CR20/CR20W)
Addition of “Also, TM2/TM2W can be cleared after capture operation” to (b) When specified
as capture register in (3) Capture/compare register (CR21/CR21W)
Correction of timing of TM2 in Figure 10-11 Timer/Counter 2 External Event Count Timing
Change from “the output level at the time it was stopped is retained” to “the inactive level
(ALVn: n = 0, 1) is output” when timer/counter 2 is stopped by timer control register 1
Change from “the output level at the time it was stopped is retained” to “the active level is
output” when timer/counter 2 is stopped by timer control register 1
time calculation method
CLK
(19 s) to 180/f
Contents Revised from the Previous Edition
CLK
= 12.5 MHz)
APPENDIX E RIVISION HISTORY
CLK
(14.4 s)
CHAPTER 1
GENERAL
CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 8
TIMER/COUNTER
0
CHAPTER 9 TIMER/
COUNTER 1
CHAPTER 10
TIMER/COUNTER
2
CHAPTER 11
TIMER 3
CHAPTER 12
WATCHDOG
TIMER FUNCTION
CHAPTER 14 A/D
CONVERTER
CHAPTER 16
ASYNCHRONOUS
SERIAL INTER-
FACE/3-WIRE
SERIAL I/O
CHAPTER 18
CLOCK OUTPUT
FUNCTION
CHAPTER 20
INTERRUPT
FUNCTIONS
Applied to
(3/4)
717