MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 9

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MSC8103M1100

Manufacturer Part Number
MSC8103M1100
Description
Network Processor, Networking Digital Signal Processor
Manufacturer
Motorola / Freescale Semiconductor
Datasheet

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1.3 Clock Signals
CLKIN
MODCK1
TC0
BNKSEL0
MODCK2
TC1
BNKSEL1
MODCK3
TC2
BNKSEL2
CLKOUT
DLLIN
Signal
Name
Input
Input
Output
Output
Input
Output
Output
Input
Output
Output
Output
Input
Type
Clock In
Primary clock input to the MSC8101 PLL.
Clock Mode Input 1
Defines the operating mode of internal clock circuits.
Transfer Code 0
Supplies information that can be useful for debugging bus transactions initiated by the
MSC8101.
Bank Select 0
Selects the SDRAM bank when the MSC8101 is in 60x-compatible bus mode.
Clock Mode Input 2
Defines the operating mode of internal clock circuits.
Transfer Code 1
Supplies information that can be useful for debugging bus transactions initiated by the
MSC8101.
Bank Select 1
Selects the SDRAM bank when the MSC8101 is in 60x-compatible bus mode.
Clock Mode Input 3
Defines the operating mode of internal clock circuits.
Transfer Code 2
Supplies information that can be useful for debugging bus transactions initiated by the
MSC8101.
Bank Select 2
Selects the SDRAM bank when the MSC8101 is in 60x-compatible bus mode.
Clock Out
The system bus clock.
DLLIN
Synchronizes with an external device.
Table 1-2. Clock Signals
Signal Description
Clock Signals
1-5

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