MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 56

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

Clock Configuration
2-6
2.6.2.2 System Clock Mode Register
RESET
RESET
SCMR is a read-only register that is updated during power-on reset (PORESET) and provides the mode
control signals to the PLLs, DLL, and clock logic. This register reflects the currently defined
configuration settings. For details of the available setting options, see AN2306/D.
TYPE
TYPE
COREPDF
SPLLPDF
COREMF
Bit No.
CPMDF
BUSDF
Name
12–15
16–19
8–11
0–3
4–7
Bit 0
16
Configuration
Configuration
Configuration
Configuration
Configuration
PORESET
COREPDF
SPLLPDF
17
1
Pins
Pins
Pins
Pins
Pins
Figure 2-2. System Clock Mode Register (SCMR)—0x10C88
Defaults
18
2
Unaffected Core PLL Pre-Division Factor
Unaffected Core Multiplication Factor
Unaffected 60x-compatible Bus Division Factor
Unaffected CPM Division Factor
Unaffected SPLL Pre-Division Factor
19
3
Reset
Hard
Table 2-8. SCMR Field Descriptions
20
4
COREMF
21
SPLLMF
5
22
6
23
Description
7
—
—
R
R
24
—
8
DLLDIS
25
9
BUSDF
10
26
—
0000
0001
0010
0011
All other combinations not used.
0101
0110
0111
All other combinations not used.
0001
0010
0011
0100
0101
All other combinations not used.
0000
0001
0010
All other combinations not used.
0000
0001
0010
0011
0100
0101
All other combinations not used
11
27
12
28
CPLL PDF = 1
CPLL PDF = 2
CPLL PDF = 3
CPLL PDF = 4
CPLL MF = 10
CPLL MF = 12
CPLL MF = 14
Bus DF = 2
Bus DF = 3
Bus DF = 4
Bus DF = 5
Bus DF = 6
CPM DF = 1
CPM DF = 2
CPM DF = 3
SPLL PDF = 1
SPLL PDF = 2
SPLL PDF = 3
SPLL PDF = 4
SPLL PDF = 5
SPLL PDF = 6
Settings
COREDF
13
29
CPMDF
14
30
15
31