MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 65

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

Notes:
No.
31a
31b
32a
32b
33a
33b
35a
35b
35d
31c
32c
35c
34
36
TA delay from the 50% level of the REFCLK rising edge
•
•
TEA delay from the 50% level of the REFCLK rising edge
•
•
PSDVAL delay from the 50% level of the REFCLK rising edge
•
•
Address bus delay from the 50% level of the REFCLK rising edge
•
•
Address attributes: TT/TBST/TSIZ/GBL delay from the 50% level of the
REFCLK rising edge
BADDR delay from the 50% level of the REFCLK rising edge
Data bus delay from the 50% level of the REFCLK rising edge
•
•
DP delay from the 50% level of the REFCLK rising edge
•
•
Memory controller signals/ALE delay from the 50% level of the REFCLK
rising edge
DBG/BR/DBB delay from the 50% level of the REFCLK rising edge
AACK/ABB/CS delay from the 50% level of the REFCLK rising edge
BG delay from the 50% level of the REFCLK rising edge
TS delay from the 50% level of the REFCLK rising edge
Delay from the 50% level of the REFCLK rising edge for all other signals
Pipeline mode
Non-pipeline mode
Pipeline mode
Non-pipeline mode
Pipeline mode
Non-pipeline mode
Multi master mode (SIUBCR[EBM] = 1)
Single master mode (SIUBCR[EBM] = 0)
Pipeline mode
Non-pipeline mode
Pipeline mode
Non-pipeline mode
1.
2.
The maximum bus frequency depends on the mode:
• In 60x-compatible mode connected to another MSC8101 device, the frequency is determined by adding
the input and output longest timing values, which results in a frequency of 75 MHz for 30 pF output
capacitance. In multi-master mode when connected to another MSC8101 device, the frequency is
determined by adding the input and output longest timing values, which results in a frequency of 75 MHz
for 30 pF output capacitance.
• Certain bus modes, such as non-extra cycle (EXDD = 1), non-pipelined, and ECC/Parity modes, result in
slower bus frequencies.
• In single-master mode, the frequency depends on the timing of the devices connected to the MSC8101.
Output specifications are measured from the 50% level of the rising edge of REFCLK to the 50% level of
the signal. Timings are measured at the pin.
Table 2-16. AC Timing for SIU Outputs
Characteristic
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
30 pF
5.0
6.0
4.0
5.0
6.0
6.5
6.5
6.0
6.5
4.5
7.0
7.5
5.0
5.5
6.0
4.0
5.0
4.5
4.5
6.5
Maximum
50 pF
6.5
7.5
5.5
6.0
7.5
8.0
8.0
7.5
8.0
6.0
8.5
9.0
6.5
7.0
7.5
5.5
6.5
6.0
6.0
8.0
AC Timings
2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-15