MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 68

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

AC Timings
2-18
Notes:
Number
47
48
49
50
51
52
53
54
55
56
57
58
61
62
63
64
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The host request is HREQ/HREQ in the single host request mode and HRRQ/HRRQ and
11. Compute the value using the expression.
Host data input minimum setup time before write data strobe
deassertion
Host data input minimum setup time before HACK write
deassertion
Host data input minimum hold time after write data strobe
deassertion
Host data input minimum hold time after HACK write deassertion
Read data strobe minimum assertion to output data active from
high impedance
HACK read minimum assertion to output data active from high
impedance
Read data strobe maximum assertion to output data valid
HACK read maximum assertion to output data valid
Read data strobe maximum deassertion to output data high
impedance
HACK read maximum deassertion to output data high impedance
Output data minimum hold time after read data strobe
deassertion
Output data minimum hold time after HACK read deassertion
HCS[1–2] minimum assertion to read data strobe assertion
HCS[1–2] minimum assertion to write data strobe assertion
HCS[1–2] maximum assertion to output data valid
HCS[1–2] minimum hold time after data strobe deassertion
HA[0–3], HRW minimum setup time before data strobe assertion
•
•
HA[0–3], HRW minimum hold time after data strobe deassertion
Maximum delay from read data strobe deassertion to host request
deassertion for “Last Data Register” read
Maximum delay from write data strobe deassertion to host request
deassertion for “Last Data Register” write
Minimum delay from DMA HACK (OAD=0) or Read/Write data
strobe(OAD=1) deassertion to HREQ assertion.
Maximum delay from DMA HACK (OAD=0) or Read/Write data
strobe(OAD=1) assertion to HREQ deassertion
Read
Write
T
In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is
programmable.
V
The read data strobe is HRD/HRD in the dual data strobe mode and HDS/HDS in the single data
strobe mode.
In 64-bit mode, The “last data register” is the register at address $7, which is the last location to be
read or written in data transfers. This is RX0/TX0 in the little endian mode (HBE = 0), or RX3/TX3 in
the big endian mode (HBE = 1).
This timing is applicable only if a read from the “last data register” is followed by a read from the RXL,
RXM, or RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the
HREQ/HREQ signal.
This timing is applicable only if two consecutive reads from one of these registers are executed.
The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.
The data strobe is host read (HRD/HRD) or host write (HWR/HWR) in the dual data strobe mode and
host data strobe (HDS/HDS) in the single data strobe mode.
HTRQ/HTRQ in the double host request mode. HRRQ/HRRQ is deasserted only when HOTX fifo is
empty, HTRQ/HTRQ is deasserted only if HORX fifo is full (treat as level Host Request).
C
CC
= 1/ DSPCLK. At 300 MHz, T
= 3.3 V ± 0.3 V; T
Table 2-18. Host Interface (HDI16) Timing
4
8
8
4
4
Characteristics
J
= –40°C to +100 °C, C
C
= 3.3 ns
4, 5, 10
5,8,10
3
L
= 50 pF
4
4
9
8
9
1, 2
9
(Continued)
(2.0
(3.5
(4.0
(3.5
Expression
(2.5
T
C
T
T
—
—
—
—
—
—
—
—
—
—
T
T
+ 5.0
T
C
C
C
C
C
) + 5.0
) + 5.0
) + 5.0
) + 5.0
) + 5
Note 11
Note 11
Note 11
Note 11
Note 11
Note 11
Value
5.0
5.0
5.0
5.0
5.0
5.0
5.0
0.0
5.0
5.0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns