MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 43

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

General-
Purpose
PC6
PC5
I/O
SI2: L1ST2
FCC1: CD
HDLC serial, HDLC nibble,
and transparent
FCC1: RXADDR2
UTOPIA master
FCC1: RXADDR2
UTOPIA slave
FCC1: RXCLAV1
UTOPIA multi-PHY master,
direct polling
SMC1: SMTXD
SI2: L1ST3
FCC2: CTS
HDLC serial, HDLC nibble,
and transparent
Peripheral Controller:
Name
Dedicated I/O
Protocol
Table 1-5. Port C Signals (Continued)
Dedicated
Direction
I/O Data
Output
Output
Output
Output
Input
Input
Input
Input
Communications Processor Module (CPM) Ports
Serial Interface 2: Layer 1 Strobe 2
In the time-slot assigner supported by SI2. The MSC8103
time-slot assigner supports up to four strobe outputs that can
be asserted on a bit or byte basis. The strobe outputs are
useful for interfacing to other devices that do not support the
multiplexed interface or for enabling/disabling three-state I/O
buffers in a multiple-transmitter architecture. These strobes
can also generate output wave forms for such applications as
stepper-motor control.
FCC1: Carrier Detect
In the standard modem interface signals supported by FCC1
(RTS, CTS, and CD). CD is an input asynchronous with the
data.
FCC1: UTOPIA Multi-PHY Master Receive Address Bit 2
In the ATM UTOPIA master interface supported by FCC1, this
is receive address bit 2.
FCC1: UTOPIA Slave Receive Address Bit 2
In the ATM UTOPIA slave interface supported by FCC1 using
multiplexed polling, this is receive address bit 2.
FCC1: UTOPIA Multi-PHY Master Receive Cell Available 1
Direct Polling
In the ATM UTOPIA master interface supported by FCC1
using direct polling, RXCLAV1 is asserted by an external PHY
when one complete ATM cell is available for transfer.
SMC1: Transmit Data
Supported by SMC1. The SMC interface consists of SMTXD,
SMRXD, SMSYN, and a clock. Not all signals are used for all
applications. SMCs are full-duplex ports that supports three
protocols or modes: UART, transparent, or general-circuit
interface (GCI).
Serial Interface 2: Layer 1 Strobe 3
In the time-slot assigner supported by SI2. The MSC8103
time-slot assigner supports up to four strobe outputs that can
be asserted on a bit or byte basis. The strobe outputs are
useful for interfacing to other devices that do not support the
multiplexed interface or for enabling/disabling three-state I/O
buffers in a multiple-transmitter architecture. These strobes
can also generate output wave forms for such applications as
stepper-motor control.
FCC2: Clear To Send
In the standard modem interface signals supported by FCC2
(RTS, CTS, and CD). CTS is asynchronous with the data.
Description
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