MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 45

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

1.7.4 Port D Signals
General-
Purpose
PD31
PD30
PD29
I/O
SCC1: RXD
DMA: DRACK1
DMA: DONE1
SCC1: TXD
DMA: DRACK2
DMA: DONE2
SCC1: RTS, TENA
FCC1: RXADDR3
UTOPIA master
FCC1: RXADDR3
UTOPIA slave
FCC1: RXCLAV2
UTOPIA multi-PHY master,
direct polling
Peripheral Controller:
Name
Dedicated I/O
Protocol
Table 1-6. Port D Signals
Dedicated
Direction
I/O Data
Output
Output
Output
Output
Output
Output
Output
Input/
Input/
Input
Input
Input
Communications Processor Module (CPM) Ports
SCC1: Receive Data
Supported by SCC1. SCC1 receives serial data from RXD.
DMA: Data Request Acknowledge 1
DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU
DMA. DONE1 and DRACK1 are signals on the same pin
and therefore cannot be used simultaneously. There are
two sets of DMA pins associated with the PIO ports.
DMA: Done 1
DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU
DMA. DONE1 and DRACK1 are signals on the same pin
and therefore cannot be used simultaneously. There are
two sets of DMA pins associated with the PIO ports.
SCC1: Transmit Data
Supported by SCC1. SCC1 transmits serial data out of
TXD.
DMA: Data Request Acknowledge 2
DACK2, DREQ2, DRACK2, and DONE2 belong to the SIU
DMA. DONE2 and DRACK2 are signals on the same pin
and therefore cannot be used simultaneously. There are
two sets of DMA pins associated with the PIO ports.
DMA: Done 2
DACK2, DREQ2, DRACK2, and DONE2 belong to the SIU
DMA. DONE2 and DRACK2 are signals on the same pin
and therefore cannot be used simultaneously. There are
two sets of DMA pins associated with the PIO ports.
SCC1: Request to Send, Transmit Enable
Typically used in conjunction with CD supported by SCC2.
The MSC8103 SCC1 transmitter requests the receiver to
send data by asserting RTS low. The request is accepted
when CTS is returned low. TENA is the signal used in
Ethernet mode.
FCC1: UTOPIA Multi-PHY Master Receive Address Bit 3
In the ATM UTOPIA master interface supported by FCC1
using multiplexed polling, this is receive address bit 3.
FCC1: UTOPIA Slave Receive Address Bit 3
In the ATM UTOPIA slave interface supported by FCC1
using multiplexed polling, this is receive address bit 3.
FCC1: UTOPIA Multi-PHY Master Receive Cell Available
2 Direct Polling
In the ATM UTOPIA master interface supported by FCC1
using direct polling, RXCLAV2 is asserted by an external
PHY when one complete ATM cell is available for transfer.
Description
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