MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 67

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

2.7.4 HDI16 Signals
2.7.3.2 DMA Data Transfers
Table 2-17 describes the DMA signal timing.
The DREQ
edge of
the timings in Table 2-17. Figure 2-7 shows synchronous peripheral interaction.
Number
Number
44a
44b
44c
45
46
72
73
74
75
76
REFCLK
Read data strobe minimum assertion width
HACK read minimum assertion width
Read data strobe minimum deassertion width
HACK read minimum deassertion width
Read data strobe minimum deassertion width
Register” reads
reads
HACK minimum deassertion width after “Last Data Register”
reads
Write data strobe minimum assertion width
HACK write minimum assertion width
Write data strobe minimum deassertion width
HACK write minimum deassertion width after ICR, CVR and Data
Register writes
signal is synchronized with the falling edge of
DREQ setup time before REFCLK falling edge
DREQ hold time after REFCLK falling edge
DONE setup time before REFCLK rising edge
DONE hold time after REFCLK rising edge
DACK/DRACK/DONE delay after REFCLK rising edge
7
5,6
. To achieve fast response, a synchronized peripheral should assert
DACK/DONE/DRACK Outputs
5
5,6
Table 2-18. Host Interface (HDI16) Timing
, or between two consecutive CVR, ICR, or ISR
Characteristics
Characteristic
DONE Input
Table 2-17. DMA Signals
Figure 2-7. DMA Signals
REFCLK
DREQ
3
8
4
74
8
4
4
after “Last Data
REFCLK
.
76
DONE
72
Minimum
(1.5
(2.5
(1.5
(2.5
75
Expression
1, 2
timing is relative to the rising
0.5
0.5
0.5
T
6
9
C
T
T
T
T
+ 5.0
C
C
C
C
) + 5.0
) + 5.0
) + 5.0
) + 5.0
DREQ
Maximum
—
—
—
—
9
Note 11
Note 11
Note 11
Note 11
Note 11
Value
AC Timings
according to
73
Units
Unit
ns
ns
ns
ns
ns
2-17
ns
ns
ns
ns
ns