MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 26

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

Communications Processor Module (CPM) Ports
1-22
General-
Purpose
PA20
PA19
PA18
PA17
I/O
FCC1: TXD5
UTOPIA
FCC1: TXD2
MII and HDLC nibble
FCC1: TXD6
UTOPIA
FCC1: TXD1
MII and HDLC nibble
FCC1: TXD7
UTOPIA
FCC1: TXD0
MII and HDLC nibble
FCC1: TXD
HDLC serial and transparent
FCC1: RXD7
UTOPIA
FCC1: RXD0
MII and HDLC nibble
FCC1: RXD
HDLC serial and transparent
Peripheral Controller:
Name
Dedicated Signal
Protocol
Table 1-3. Port A Signals (Continued)
Dedicated
Direction
I/O Data
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
FCC1: UTOPIA Transmit Data Bit 5
TXD[0–7] is part of the ATM UTOPIA interface supported by
FCC1. The MSC8103 outputs ATM cell octets (UTOPIA
interface data) on TXD[0–7]. TXD7 is the most significant
bit. TXD0 is the least significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
FCC1: MII and HDLC Nibble Transmit Data Bit 2
TXD[3–0] is supported by MII and HDLC nibble modes in
FCC1. TXD3 is the most significant bit. TXD0 is the least
significant bit.
FCC1: UTOPIA Transmit Data Bit 6
TXD[0–7] is part of the ATM UTOPIA interface supported by
FCC1. The MSC8103 outputs ATM cell octets (UTOPIA
interface data) on TXD[0–7]. TXD7 is the most significant
bit. TXD0 is the least significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
FCC1: MII and HDLC Nibble Transmit Data Bit 1
TXD[3–0] is supported by MII and HDLC transparent nibble
modes in FCC1. TXD3 is the most significant bit. TXD0 is
the least significant bit.
FCC1: UTOPIA Transmit Data Bit 7.
TXD[0–7] is part of the ATM UTOPIA interface supported by
FCC1. The MSC8103 outputs ATM cell octets (UTOPIA
interface data) on TXD[0–7]. TXD7 is the most significant
bit. TXD0 is the least significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
FCC1: MII and HDLC Nibble Transmit Data Bit 0
TXD[3–0] is supported by MII and HDLC nibble modes in
FCC1. TXD3 is the most significant bit. TXD0 is the least
significant bit.
FCC1: HDLC Serial and Transparent Transmit Data Bit
The TXD serial bit is supported by HDLC serial and
transparent modes in FCC1.
FCC1: UTOPIA Receive Data Bit 7.
RXD[0–7] is part of the ATM UTOPIA interface supported
by FCC1. The MSC8103 inputs ATM cell octets (UTOPIA
interface data) on RXD[0–7]. RXD7 is the most significant
bit. RXD0 is the least significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes. To
support Multi-PHY configurations, RXD[0–7] is tri-stated,
enabled only when RXENB is asserted.
FCC1: MII and HDLC Nibble Receive Data Bit 0
RXD[3–0] is supported by MII and HDLC nibble mode in
FCC1. RXD3 is the most significant bit. RXD0 is the least
significant bit.
FCC1: HDLC Serial and Transparent Receive Data Bit
The RXD serial bit is supported by HDLC and transparent
by FCC1.
Description