MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 32

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

Communications Processor Module (CPM) Ports
1-28
General-
Purpose
PB25
PB24
PB23
I/O
FCC2: TXD3
MII and HDLC nibble
SI1 TDMA1: L1TXD3
TDM nibble
SI2 TDMC2: L1TSYNC
TDM serial
FCC2: TXD2
MII and HDLC nibble
SI1 TDMA1: L1RXD3
nibble
SI2 TDMC2: L1RSYNC
serial
FCC2: TXD1
MII and HDLC nibble
SI1 TDMA1: L1RXD2
TDM nibble
SI2 TDMD2: L1TXD
TDM serial
Peripheral Controller:
Name
Dedicated I/O
Protocol
Table 1-4. Port B Signals (Continued)
Dedicated
Direction
I/O Data
Output
Output
Output
Output
Output
Input
Input
Input
Input
FCC2: MII and HDLC Nibble Transmit Data Bit 3
Supported by MII and HDLC nibble mode in FCC2. TXD3 is
the most significant bit. TXD0 is the least significant bit.
Time-Division Multiplexing A1: Nibble Layer 1 Transmit
Data Bit 3
TDMA1 transmits nibble data out of L1TXD[0–3]. L1TXD3 is
the most significant bit and L1TXD0 is the least significant
bit in nibble mode.
Time-Division Multiplexing C2: Layer 1 Transmit
Synchronization
In the TDMC2 interface supported by SI2, this is the
synchronizing signal for the transmit channel. See the Serial
Interface with Time-Slot Assigner chapter in the MSC8103
Technical Reference manual.
FCC2: MII and HDLC Nibble: Transmit Data Bit 2
Supported by MII and HDLC nibble mode in FCC2. TXD3 is
the most significant bit. TXD0 is the least significant bit.
Time-Division Multiplexing A1: Nibble Layer 1 Receive
Data Bit 3
TDMA1 receives nibble data into L1RXD[0–3]. L1RXD3 is
the most significant bit and L1RXD0 is the least significant
bit in nibble mode.
Time-Division Multiplexing C2: Layer 1 Receive
Synchronization
In the TDMC2 interface supported by SI2, this is the
synchronizing signal for the receive channel.
FCC2: MII and HDLC Nibble: Transmit Data Bit 1
Supported by MII and HDLC nibble mode in FCC2. TXD3 is
the most significant bit. TXD0 is the least significant bit.
Time-Division Multiplexing A1: Nibble Layer 1 Receive
Data Bit 2
In the TDMA1 interface supported by SI1. TDMA1 supports
bit and nibble modes. L1RXD3 is the most significant bit.
L1RXD0 is the least significant bit in nibble mode. TDMA1
receives nibble data from L1RXD[0–3].
Time-Division Multiplexing D2: Layer 1 Transmit Data
In the TDMD2 interface supported by SI2. L1TXD supports
serial mode. TDMA1 transmits serial data out of L1TXD.
Description