MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 18

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

System Bus, HDI16, and Interrupt Signals
1-14
IRQ4
DP4
DREQ3
EXT_BG3
IRQ5
DP5
DREQ4
EXT_DBG3
IRQ6
DP6
DACK3
IRQ7
DP7
DACK4
TA
Signal
Table 1-4.
Input
Input/Output
Input
Output
Input
Input/Output
Input
Output
Input
Input/Output
Output
Input
Input/Output
Output
Input/Output
Data Flow
System Bus, HDI16, and Interrupt Signals (Continued)
Interrupt Request 4
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Data Parity 4
The agent that drives the data bus also drives the data parity signals. The value
driven on the data parity four pin should give odd parity (odd number of ones) on
the group of signals that includes data parity 4 and D[32–39].
DMA Request 3
An external peripheral uses this pin to request DMA service.
External Bus Grant 3
The MSC8101 asserts this pin to grant bus ownership to an external bus master.
Interrupt Request 5
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Data Parity 5
The agent that drives the data bus also drives the data parity signals. The value
driven on the data parity five pin should give odd parity (odd number of ones) on
the group of signals that includes data parity 5 and D[40–47].
DMA Request 4
An external peripheral uses this pin to request DMA service.
External Data Bus Grant 3
The MSC8101 asserts this pin to grant data bus ownership to an external bus
master.
Interrupt Request 6
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Data Parity 6
The agent that drives the data bus also drives the data parity signals. The value
driven on the data parity six pin should give odd parity (odd number of ones) on the
group of signals that includes data parity 6 and D[48–55].
DMA Acknowledge 3
The DMA drives this output to acknowledge the DMA transaction on the bus.
Interrupt Request 7
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Data Parity 7
The master or slave that drives the data bus also drives the data parity signals. The
value driven on the data parity seven pin should give odd parity (odd number of
ones) on the group of signals that includes data parity 7 and D[56–63].
DMA Acknowledge
The DMA drives this output to acknowledge the DMA transaction on the bus.
Transfer Acknowledge
Indicates that a data beat is valid on the data bus. For single beat transfers,
assertion of TA indicates the termination of the transfer. For burst transfers, TA is
asserted four times to indicate the transfer of four data beats with the last assertion
indicating the termination of the burst transfer.
1
1
1
1
1
1
1
1
1
1
1
1
1,2
1,2
Description