MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 16

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

System Bus, HDI16, and Interrupt Signals
1-12
D56
HACK/HACK
HRRQ/HRRQ
D57
HDSP
D58
HDDS
D59
H8BIT
D60
HCS2
D[61–63]
Reserved
Signal
Table 1-4.
Input/Output
Output
Output
Input/Output
Input
Input/Output
Input
Input/Output
Input
Input/Output
Input
Input/Output
Data Flow
System Bus, HDI16, and Interrupt Signals (Continued)
Data Bus Bit 56
In write transactions the bus master drives the valid data on this pin. In read
transactions the slave drives the valid data on this pin.
Host Acknowledge
When the HDI16 is programmed to interface with a single host request host bus,
this pin is the host acknowledge Schmitt trigger input (HACK). The polarity of the
host acknowledge is programmable.
Receive Host Request
When the HDI16 is programmed to interface with a double host request host bus,
this pin is the receive host request output (HRRQ/HRRQ). The signal can be
programmed as driven or open drain. The polarity of the host request is
programmable.
Data Bus Bit 57
In write transactions the bus master drives the valid data on this pin. In read
transactions the slave drives the valid data on this pin.
Host Data Strobe Polarity
When the HDI16 interface is enabled, this pin is the host data strobe polarity
(HDSP).
Data Bus Bit 58
In write transactions the bus master drives the valid data on this pin. In read
transactions the slave drives the valid data on this pin.
Host Dual Data Strobe
When the HDI16 interface is enabled, this pin is the host dual data strobe (HDDS).
Data Bus Bit 59
In write transactions the bus master drives the valid data on this pin. In read
transactions the slave drives the valid data on this pin.
H8BIT
When the HDI16 interface is enabled, this bit determines if the interface is in 8-bit
or 16-bit mode.
Data Bus Bit 60
In write transactions the bus master drives the valid data on this pin. In read
transactions the slave drives the valid data on this pin.
Host Chip Select
When the HDI16 interface is enabled, this is one of the two chip-select pins. The
HDI16 chip select is a logical OR of HCS1 and HCS2.
Data Bus Bits 61–63
Used only in 60x-mode-only mode. In write transactions the bus master drives the
valid data on this bus. In read transactions the slave drives the valid data on this
bus.
These dedicated signals are reserved when the HDI16 is enabled.
3
3
3
3
3
3
Description
3