MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 59

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

2.7.2 Reset Timing
The MSC8103 has several inputs to the reset logic:
• Power-on reset (
• External hard reset (
• External soft reset (
Asserting an external
and
configuration pins:
•
•
•
•
All these reset sources are fed into the reset controller, which takes different actions depending on the
source of the reset. The reset status register indicates the last sources to cause a reset. Table 2-11
describes reset causes.
2.7.2.1 Reset Operation
The reset control logic determines the cause of a reset, synchronizes it if necessary, and resets the
appropriate logic modules. The memory controller, system protection logic, interrupt controller, and
parallel I/O pins are initialized only on hard reset. Soft reset initializes the internal logic while
maintaining the system configuration. The MSC8103 has three mechanisms for reset configuration: host
reset configuration, hardware reset configuration, and reduced reset configuration.
2.7.2.2 Power-On Reset Flow
Asserting the
externally for at least 16 input clock cycles after external power to the MSC8103 reaches at least 2/3
V
the SC140 core EONCE Event (
pins are sampled at the rising edge of
(
in the Hard Reset Configuration Word determine the PLL locking mode, by defining the ratio between
the DSP clock, the bus clocks, and the CPM clock frequencies.
MODCK[1–3]
Power-on reset
(PORESET)
Hard reset
(HRESET)
Soft reset
(SRESET)
CC
RSTCONF
DBREQ
HPE
BTM[0–1]
SRESET
. As Table 2-12 shows, the MSC8103 has five configuration pins, four of which are multiplexed with
Name
—disable (0) or enable (1) the host port (HDI16)
—determines whether to operate in normal mode (0) or invoke the SC140 debug mode (1)
—boot from external memory (00) or the HDI16 (01)
. When the external
—determines whether the MSC8103 is a master (0) or slave (1) device
PORESET
) pins are sampled by the MSC8103. The signals on these pins and the MODCK_H value
PORESET
Input/Output
Input/Output
Direction
PORESET
SRESET
HRESET
Input
external pin initiates the power-on reset flow.
)
)
)
EE[0–1]
causes concurrent assertion of an internal
PORESET
PORESET initiates the power-on reset flow that resets all the MSC8103s and
configures various attributes of the MSC8103, including its clock mode.
The MSC8103 can detect an external assertion of HRESET only if it occurs
while the MSC8103 is not asserting reset. During HRESET, SRESET is
asserted. HRESET is an open-drain pin.
The MSC8103 can detect an external assertion of SRESET only if it occurs
while the MSC8103 is not asserting reset. SRESET is an open-drain pin.
Table 2-11. Reset Causes
PORESET
,
EE[4–5]
signal is deasserted, the MSC8103 samples several
. In addition to these configuration pins, three
) pins and the fifth of which is the
Description
PORESET
PORESET
should be asserted
RSTCONF
signal,
AC Timings
HRESET
pin. These
2-9
,