MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 54

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

Clock Configuration
2.6 Clock Configuration
2.6.1 Valid Clock Modes
2-4
The following sections provide a general description of clock configuration.
Table 2-6 shows the maximum frequency values for each rated core frequency (250, 275, or 300 MHz).
The user must ensure that maximum frequency values are not exceeded.
Six bit values map the MSC8101 clocks to one of the valid configuration mode options. Each option
determines the
values are derived from three dedicated input pins (
configuration word (MODCK_H). To configure the SPLL pre-division factor, SPLL multiplication
factor, and the frequencies for the SC140 core, SCC clocks, CPM parallel I/O ports, and system buses,
the
power-on reset (internal
PORESET
• SPLL pre-division factor (SPLL PDF)
• SPLL multiplication factor (SPLL MF)
• Bus post-division factor (Bus DF)
• CPM division factor (CPM DF)
• Core division factor (Core DF)
• CPLL pre-division factor (CPLL PDF)
• CPLL multiplication factor (CPLL MF)
The SCC division factor (SCC DF) is fixed at 4. The BRG division factor (BRG DF) is configured
through the System Clock Control Register (SCCR) and can be 4, 16 (default after reset), 64, or 256.
Note:
Core Frequency
CPM Frequency (CPMCLK)
Bus Frequency (BCLK)
Serial Communication Controller Clock Frequency (SCLK)
Baud Rate Generator Clock Frequency (BRGCLK)
External Clock Output Frequency (CLKOUT)
Core power dissipation at 300 MHz
CPM power dissipation at 200 MHz
SIU power dissipation at 100 MHz
Core leakage power
CPM leakage power
SIU leakage power
MODCK[1–3]
Refer to AN2306/D Clock Mode Selection for MSC8101 and MSC8103 Mask Set 1K87M for
details on clock configuration.
signal is deasserted. The following factors are configured:
CLKIN
pins are sampled and combined with the MODCK_H values when the internal
, SC140 core, system bus, SCC clock, CPM, and
Characteristic
PORESET
Characteristic
Table 2-5. Typical Power Dissipation
Table 2-6. Maximum Frequencies
) is deasserted. Clock configuration changes only when the internal
MODCK[1–3]
) and three bits from the hard reset
166.67
83.33
83.33
83.33
83.33
250
Maximum Frequency in MHz
CLKOUT
Symbol
P
P
P
P
P
P
CORE
CPM
LCO
LCP
SIU
LSI
183.33
91.67
91.67
91.67
91.67
frequencies. The six bit
275
Typical
350
320
80
3
6
2
300
200
100
100
100
100
Unit
mW
mW
mW
mW
mW
mW