MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 58
MSC8103M1100
Manufacturer Part Number
MSC8103M1100
Description
Network Processor, Networking Digital Signal Processor
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
1.MSC8103M1100.pdf
(120 pages)
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AC Timings
2.7 AC Timings
2.7.1 Clocking and Timing Characteristics
2-8
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs
and inputs. AC timings are based on a 50 pF load, except where noted otherwise, and 50
line.
Phase Jitter between BCLK and DLLIN
CLKIN frequency
CLKIN slope
DLLIN slope
CLKOUT frequency jitter
Delay between CLKOUT and DLLIN
Notes:
Input Clock
SPLL MF Clock
Bus
Output
Serial Communications Controller
Communications Processor
Module
SC140 Core
Baud Rate Generator
•
•
•
•
For BRG DF = 4
For BRG DF = 16 (default)
For BRG DF = 64
For BRG DF = 256
1.
2.
Clock
Low CLKIN frequency causes poor PLL performance. Choose a CLKIN frequency high enough to keep
the frequency after the predivider (SPLLMFCLK) higher than 18 MHz.
CLKIN should have a 50%
1,2
Characteristic
Table 2-9. System Clock Parameters
SPLLMFCLK
CPMCLK
Symbol
CLKOUT
DSPCLK
BRGCLK
CLKIN
BCLK
SCLK
Table 2-10. Clock Ranges
5% duty cycle.
562.5 KHz
43.2 MHz
2.25 MHz
18 MHz
18 MHz
18 MHz
18 MHz
36 MHz
72 MHz
36 MHz
9 MHz
Min
All
Minimum
18
—
—
—
—
—
Maximum Rated Core Frequency
Max. Values for SC140 Clock Rating of:
166.7 MHz
20.83 MHz
250 MHz
83.3 MHz
83.3 MHz
83.3 MHz
83.3 MHz
5.21 MHz
250 MHz
1.3 MHz
20.83
62.5
(0.01
CLKOUT) + CLKIN jitter
Maximum
68.75 MHz
91.67 MHz
91.67 MHz
91.67 MHz
183.3 MHz
91.67 MHz
22.91 MHz
275 MHz
22.9 MHz
5.73 MHz
1.43 MHz
275 MHz
0.5
75
5
2
5
transmission
300 MHz
6.25 MHz
1.56 MHz
100 MHz
100 MHz
100 MHz
200 MHz
300 MHz
100 MHz
75 MHz
25 MHz
25 MHz
Unit
MHz
ns
ns
ns
ns
ns
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