MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 27

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

General-
Purpose
PA16
PA15
PA14
PA13
I/O
FCC1: RXD6
UTOPIA
FCC1: RXD1
MII and HDLC nibble
FCC1: RXD5
UTOPIA
RXD2
MII and HDLC nibble
FCC1: RXD4
UTOPIA
FCC1: RXD3
MII and HDLC nibble
FCC1: RXD3
UTOPIA
SDMA: MSNUM2
Peripheral Controller:
Name
Dedicated Signal
Protocol
Table 1-3. Port A Signals (Continued)
Dedicated
Direction
I/O Data
Output
Input
Input
Input
Input
Input
Input
Input
Communications Processor Module (CPM) Ports
FCC1: UTOPIA Receive Data Bit 6.
RXD[0–7] is part of the ATM UTOPIA interface supported
by FCC1. The MSC8103 inputs ATM cell octets (UTOPIA
interface data) on RXD[0–7]. RXD7 is the most significant
bit. RXD0 is the least significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes. To
support Multi-PHY configurations, RXD[0–7] is tri-stated,
enabled only when RXENB is asserted.
FCC1: MII and HDLC Nibble Receive Data Bit 1
RXD[3–0] is supported by MII and HDLC nibble mode in
FCC1. RXD3 is the most significant bit. RXD0 is the least
significant bit.
FCC1: UTOPIA Receive Data Bit 5
In the ATM UTOPIA interface supported by FCC1. The
MSC8103 inputs ATM cell octets (UTOPIA interface data)
on RXD[0–7]. RXD7 is the most significant bit. RXD0 is the
least significant bit. When no ATM data is available, idle
cells are inserted. A cell is 53 bytes. To support Multi-PHY
configurations, RXD[0–7] is tri-stated, enabled only when
RXENB is asserted.
FCC1: MII and HDLC Nibble Receive Data Bit 2
RXD[3–0] is supported by MII and HDLC nibble mode in
FCC1. RXD3 is the most significant bit. RXD0 is the least
significant bit.
FCC1: UTOPIA Receive Data Bit 4.
In the ATM UTOPIA interface supported by FCC1. The
MSC8103 inputs ATM cell octets (UTOPIA interface data)
on RXD[0–7]. RXD7 is the most significant bit. RXD0 is the
least significant bit. When no ATM data is available, idle
cells are inserted. A cell is 53 bytes. To support Multi-PHY
configurations, RXD[0–7] is tri-stated, enabled only when
RXENB is asserted.
FCC1: MII and HDLC Nibble Receive Data Bit 3
RXD[3–0] is supported by MII and HDLC nibble mode in
FCC1. RXD3 is the most significant bit. RXD0 is the least
significant bit.
FCC1: UTOPIA Receive Data Bit 3
In the ATM UTOPIA interface supported by FCC1. The
MSC8103 inputs ATM cell octets (UTOPIA interface data)
on RXD[0–7]. RXD7 is the most significant bit. RXD0 is the
least significant bit. A cell is 53 bytes. To support Multi-PHY
configurations, RXD[0–7] is tri-stated, enabled only when
RXENB is asserted.
Module Serial Number Bit 2
MSNUM[0–4] is the sub-block code of the current peripheral
controller using SDMA. MSNUM5 indicates which section,
transmit (0) or receive (1), is active during the transfer.
Description
1-23