MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet

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Technical Data Advance Information MSC8103/D Rev. 1, 7/2003 Networking Digital Signal Processor (mask set 1K87M) CPM UTOPIA Interface MII • { • TDMs • The Motorola MSC8103 16-bit Digital Signal Processor (DSP) is the Other Peripherals first member of the ...

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Table of Contents MSC8103 Features............................................................................................................................................. iii Target Applications ............................................................................................................................................ iv Product Documentation...................................................................................................................................... iv Chapter 1 Signal/ Connection Descriptions 1.1 Signal Groupings.............................................................................................................................................. 1-1 1.2 Power Signals................................................................................................................................................... 1-4 1.3 Clock Signals ................................................................................................................................................... 1-5 1.4 Reset, Configuration, and EOnCE Event Signals ............................................................................................ 1-6 ...

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MSC8103 Features • SC140 Core — Architecture optimized for efficient C/C++ code compilation — Four 16-bit ALUs and two 32-bit AGUs — 1200 DSP MMACS running at 300 MHz — Very low power dissipation—less than 0.25 W for the core ...

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Target Applications The MSC8103 targets applications requiring very high performance, very large amounts of on-chip memory, and such networking capabilities as: • Third-generation wideband wireless infrastructure systems • Packet Telephony systems • Multi-channel modem banks • Multi-channel xDSL Product Documentation ...

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Chapter 1 Signal/ Connection Descriptions 1.1 Signal Groupings The MSC8103 external signals are organized into functional groups, as shown in Table 1-1, Figure 1-1, and Figure 1-2. Table 1-1 lists the functional groups, the number of signal connections in each ...

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Signal Groupings For the signals multiplexed on Ports A–D, see Figure 1-2 PC[31–22, 15–12, 7–4] PD[31–29, 19–16, 7] EOnCE Event EED EE0 EE1 EE[2–3] EE[4–5] BNKSEL[0–2] TC[0–2] SPARE1, SPARE5 Note: Refer to the System Interface Unit (SIU) chapter in the ...

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FCC1 ATM/UTOPIA FCC1 MPHY MPHY Master HDLC/ Master Ethernet HDLC mux poll transp. dir. poll MII or Slave Serial Nibble COL TXENB TXCLAV TXCLAV0 CRS RTS TXSOC (master) TX_ER RXENB TX_EN RXSOC RX_DV (slave) RXCLAV RXCLAV0 RX_ER TXD0 TXD1 TXD2 ...

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Power Signals 1.2 Power Signals Power Name DDH V CCSYN V CCSYN1 GND GND SYN GND SYN1 1-4 Table 1-1. Power and Ground Signal Inputs Description Internal Logic Power V dedicated for use with the device core. ...

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Clock Signals Signal Name CLKIN MODCK1 TC0 BNKSEL0 MODCK2 TC1 BNKSEL1 MODCK3 TC2 BNKSEL2 CLKOUT DLLIN Table 1-2. Clock Signals Type Input Clock In Primary clock input to the MSC8101 PLL. Input Clock Mode Input 1 Defines the operating ...

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Reset, Configuration, and EOnCE Event Signals 1.4 Reset, Configuration, and EOnCE Event Signals Signal Name DBREQ 1 EE0 HPE 1 EE1 1 EE2 1 EE3 1-6 Table 1-3. Reset, Configuration, and EOnCE Event Signals Type Input Debug Request Determines whether ...

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Table 1-3. Reset, Configuration, and EOnCE Event Signals (Continued) Signal Name Type BTM[0–1] Input Boot Mode 0–1 Determines the MSC8103 boot mode when PORESET is deasserted. See the Emulation and Debug chapter in the SC140 DSP Core Reference Manual for ...

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System Bus, HDI16, and Interrupt Signals 1.5 System Bus, HDI16, and Interrupt Signals The system bus, HDI16, and interrupt signals are grouped together because they use a common set of signal lines. Individual assignment of a signal to a specific ...

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Table 1-4. System Bus, HDI16, and Interrupt Signals (Continued) Signal Data Flow Reserved Output The primary configuration is reserved. BADDR29 Output Burst Address 29 One of five outputs of the memory controller. These pins connect directly to memory devices controlled ...

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System Bus, HDI16, and Interrupt Signals Signal TS AACK ARTRY DBG DBB IRQ3 D[0–31] D[32–47] HD[0–15] D[48–51] HA[0–3] 1-10 Table 1-4. System Bus, HDI16, and Interrupt Signals (Continued) Data Flow Input/Output Bus Transfer Start Signals the beginning of a new ...

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Table 1-4. System Bus, HDI16, and Interrupt Signals (Continued) Signal Data Flow D52 Input/Output Data Bus Bit 52 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data ...

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System Bus, HDI16, and Interrupt Signals Signal D56 HACK/HACK HRRQ/HRRQ D57 HDSP D58 HDDS D59 H8BIT D60 HCS2 D[61–63] Reserved 1-12 Table 1-4. System Bus, HDI16, and Interrupt Signals (Continued) Data Flow Input/Output Data Bus Bit 56 In write transactions ...

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Table 1-4. System Bus, HDI16, and Interrupt Signals (Continued) Signal Data Flow Reserved Input The primary configuration is reserved. DP0 Input/Output Data Parity 0 The agent that drives the data bus also drives the data parity signals. The value driven ...

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System Bus, HDI16, and Interrupt Signals Signal IRQ4 DP4 DREQ3 EXT_BG3 IRQ5 DP5 DREQ4 EXT_DBG3 IRQ6 DP6 DACK3 IRQ7 DP7 DACK4 TA 1-14 Table 1-4. System Bus, HDI16, and Interrupt Signals (Continued) Data Flow 1 Input Interrupt Request 4 One ...

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Table 1-4. System Bus, HDI16, and Interrupt Signals (Continued) Signal Data Flow TEA Input/Output Transfer Error Acknowledge Indicates a bus error. masters within the MSC8101 monitor the state of this pin. The MSC8101 internal bus monitor can assert this pin ...

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Memory Controller Signals 1.6 Memory Controller Signals Refer to the Memory Controller chapter in the MSC8103 Reference Manual (MSC8103RM/D) for detailed information about configuring these signals. Signal CS[0–7] BCTL1 BADDR[27–28] ALE BCTL0 PWE[0–7] PSDDQM[0–7] PBS[0–7] PSDA10 PGPL0 PSDWE PGPL1 1-16 ...

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Table 1-2. Memory Controller Signals (Continued) Data Signal Flow POE Output Bus Output Enable Output of the bus GPCM. Controls the output buffer of memory devices during read operations. PSDRAS Output Bus SDRAM RAS Output from the bus SDRAM controller. ...

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Communications Processor Module (CPM) Ports 1.7 Communications Processor Module (CPM) Ports The MSC8103 CPM supports a subset of signals included in the MPC8260. The following sections describe the functionality of the signals in the MSC8103. • The MSC8103 CPM includes ...

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Port A Signals General- Purpose I/O PA31 PA30 PA29 Communications Processor Module (CPM) Ports Table 1-3. Port A Signals Name Dedicated Peripheral Controller: I/O Data Dedicated Signal Direction Protocol FCC1: TXENB Output UTOPIA master FCC1: TXENB Input UTOPIA slave ...

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Communications Processor Module (CPM) Ports General- Purpose I/O PA28 PA27 PA26 1-20 Table 1-3. Port A Signals (Continued) Name Dedicated Peripheral Controller: I/O Data Dedicated Signal Direction Protocol FCC1: RXENB Output UTOPIA master FCC1: RXENB Input UTOPIA slave FCC1: TX_EN ...

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Table 1-3. Port A Signals (Continued) Name General- Peripheral Controller: Purpose Dedicated Signal I/O Protocol PA25 FCC1: TXD0 UTOPIA SDMA: MSNUM0 PA24 FCC1: TXD1 UTOPIA SDMA: MSNUM1 PA23 FCC1: TXD2 UTOPIA PA22 FCC1: TXD3 UTOPIA PA21 FCC1: TXD4 UTOPIA FCC1: ...

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Communications Processor Module (CPM) Ports General- Purpose I/O PA20 PA19 PA18 PA17 1-22 Table 1-3. Port A Signals (Continued) Name Dedicated Peripheral Controller: I/O Data Dedicated Signal Direction Protocol FCC1: TXD5 Output UTOPIA FCC1: TXD2 Output MII and HDLC nibble ...

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Table 1-3. Port A Signals (Continued) Name General- Peripheral Controller: Purpose Dedicated Signal I/O Protocol PA16 FCC1: RXD6 UTOPIA FCC1: RXD1 MII and HDLC nibble PA15 FCC1: RXD5 UTOPIA RXD2 MII and HDLC nibble PA14 FCC1: RXD4 UTOPIA FCC1: RXD3 ...

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Communications Processor Module (CPM) Ports General- Purpose I/O PA12 PA11 PA10 PA9 1-24 Table 1-3. Port A Signals (Continued) Name Dedicated Peripheral Controller: I/O Data Dedicated Signal Direction Protocol FCC1: RXD2 Input UTOPIA SDMA: MSNUM3 Output FCC1: RXD1 Input UTOPIA ...

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Table 1-3. Port A Signals (Continued) Name General- Peripheral Controller: Purpose Dedicated Signal I/O Protocol PA8 SMC2: SMRXD SI1 TDMA1: L1RXD0 TDM nibble SI1 TDMA1: L1RXD TDM serial PA7 SMC2: SMSYN SI1 TDMA1: L1TSYNC TDM nibble and TDM serial PA6 ...

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Communications Processor Module (CPM) Ports 1.7.2 Port B Signals General- Purpose I/O PB31 PB30 PB29 1-26 Table 1-4. Port B Signals Name Dedicated Peripheral Controller: I/O Data Dedicated I/O Direction Protocol FCC2: TX_ER Output MII SCC2: RXD Input SI2 TDMB2: ...

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Table 1-4. Port B Signals (Continued) Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PB28 FCC2: RTS HDLC serial, HDLC nibble, and transparent FCC2: RX_ER MII SCC2: RTS, TENA SI2 TDMB2: L1TSYNC TDM serial PB27 FCC2: COL MII SI2 ...

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Communications Processor Module (CPM) Ports General- Purpose I/O PB25 PB24 PB23 1-28 Table 1-4. Port B Signals (Continued) Name Dedicated Peripheral Controller: I/O Data Dedicated I/O Direction Protocol FCC2: TXD3 Output MII and HDLC nibble SI1 TDMA1: L1TXD3 Output TDM ...

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Table 1-4. Port B Signals (Continued) Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PB22 FCC2: TXD0 MII and HDLC nibble FCC2: TXD HDLC serial and transparent SI1 TDMA1: L1RXD1 TDM nibble SI2 TDMD2: L1RXD TDM serial PB21 FCC2: ...

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Communications Processor Module (CPM) Ports General- Purpose I/O PB20 PB19 PB18 1-30 Table 1-4. Port B Signals (Continued) Name Dedicated Peripheral Controller: I/O Data Dedicated I/O Direction Protocol FCC2: RXD1 Input MII and HDLC nibble SI1 TDMA1: L1TXD1 Output TDM ...

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Port C Signals General- Purpose I/O PC31 PC30 Communications Processor Module (CPM) Ports Table 1-5. Port C Signals Name Dedicated Peripheral Controller: I/O Data Dedicated I/O Direction Protocol BRG1O Output CLK1 Input TIMER1/2: TGATE1 Input BRG2O Output CLK2 Input ...

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Communications Processor Module (CPM) Ports General- Purpose I/O PC29 PC28 1-32 Table 1-5. Port C Signals (Continued) Name Dedicated Peripheral Controller: I/O Data Dedicated I/O Direction Protocol BRG3O Output CLK3 Input TIN2 Input SCC1: CTS, CLSN Input BRG4O Output CLK4 ...

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Table 1-5. Port C Signals (Continued) Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PC27 BRG5O CLK5 TIMER3/4: TGATE2 PC26 BRG6O CLK6 Timer3: TOUT3 TMCLK Communications Processor Module (CPM) Ports Dedicated I/O Data Description Direction Output Baud-Rate Generator 5 ...

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Communications Processor Module (CPM) Ports General- Purpose I/O PC25 PC24 1-34 Table 1-5. Port C Signals (Continued) Name Dedicated Peripheral Controller: I/O Data Dedicated I/O Direction Protocol BRG7O Output CLK7 Input TIN4 Input DMA: DACK2 Output BRG8O Output CLK8 Input ...

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Table 1-5. Port C Signals (Continued) Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PC23 CLK9 DMA: DACK1 EXT2 PC22 SI1: L1ST1 CLK10 DMA: DREQ1 Communications Processor Module (CPM) Ports Dedicated I/O Data Description Direction Input Clock 9 The ...

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Communications Processor Module (CPM) Ports General- Purpose I/O PC15 PC14 1-36 Table 1-5. Port C Signals (Continued) Name Dedicated Peripheral Controller: I/O Data Dedicated I/O Direction Protocol SMC2: SMTXD Output SCC1: CTS/CLSN Input FCC1: TXADDR0 Output UTOPIA master FCC1: TXADDR0 ...

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Table 1-5. Port C Signals (Continued) Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PC13 SI1: L1ST4 SCC2: CTS,CLSN FCC1:TXADDR1 UTOPIA master FCC1: TXADDR1 UTOPIA slave PC12 SI1: L1ST3 SCC2: CD, RENA FCC1: RXADDR1 UTOPIA master FCC1: RXADDR1 UTOPIA ...

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Communications Processor Module (CPM) Ports General- Purpose I/O PC7 1-38 Table 1-5. Port C Signals (Continued) Name Dedicated Peripheral Controller: I/O Data Dedicated I/O Direction Protocol SI2: L1ST1 Output FCC1: CTS Input HDLC serial, HDLC nibble, and transparent FCC1: TXADDR2 ...

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Table 1-5. Port C Signals (Continued) Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PC6 SI2: L1ST2 FCC1: CD HDLC serial, HDLC nibble, and transparent FCC1: RXADDR2 UTOPIA master FCC1: RXADDR2 UTOPIA slave FCC1: RXCLAV1 UTOPIA multi-PHY master, direct ...

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Communications Processor Module (CPM) Ports General- Purpose I/O PC4 1-40 Table 1-5. Port C Signals (Continued) Name Dedicated Peripheral Controller: I/O Data Dedicated I/O Direction Protocol SMC1: SMRXD Input SI2: L1ST4 Output FCC2: CD Input HDLC serial, HDLC nibble, and ...

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Port D Signals General- Purpose I/O PD31 PD30 PD29 Communications Processor Module (CPM) Ports Table 1-6. Port D Signals Name Dedicated Peripheral Controller: I/O Data Dedicated I/O Direction Protocol SCC1: RXD Input DMA: DRACK1 Output DMA: DONE1 Input/ Output ...

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Communications Processor Module (CPM) Ports General- Purpose I/O PD19 1-42 Table 1-6. Port D Signals (Continued) Name Dedicated Peripheral Controller: I/O Data Dedicated I/O Direction Protocol FCC1: TXADDR4 Output UTOPIA master FCC1: TXADDR4 Input UTOPIA slave FCC1: TXCLAV3 Input UTOPIA ...

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Table 1-6. Port D Signals (Continued) Name General- Peripheral Controller: Purpose Dedicated I/O I/O Protocol PD18 FCC1: RXADDR4 UTOPIA master FCC1: RXADDR4 UTOPIA slave FCC1: RXCLAV3 UTOPIA multi-PHY master, direct polling SPI: SPICLK PD17 BRG2O FCC1: RXPRTY UTOPIA SPI: SPIMOSI ...

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JTAG Test Access Port Signals General- Purpose I/O PD7 1.8 JTAG Test Access Port Signals The MSC8103 Standard Test Access Port and Boundary-Scan Architecture specification and described in Table 1-7. Signal Name TCK TDI TDO TMS TRST 1-44 Table 1-6. ...

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Reserved Signals Signal Name TEST THERM[1–2] SPARE1, 5 Table 1-8. Reserved Signals Type Input Test Used for manufacturing testing. You must connect this input to GND. — Leave disconnected. — Spare Pins Leave disconnected for backward compatibility with future ...

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Reserved Signals 1-46 ...

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Chapter 2 Specifications 2.1 Introduction This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MSC8103 communications processor. For additional information, see the MSC8103 Reference Manual. Note: The MSC8103 electrical specifications are preliminary ...

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Recommended Operating Conditions Table 2-1 describes the maximum electrical ratings for the MSC8101. Core supply voltage PLL supply voltage I/O supply voltage Input voltage Maximum operating temperature range Storage temperature range Notes: 2.3 Recommended Operating Conditions Table 2-2 lists recommended ...

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Thermal Characteristics Table 2-3 describes thermal characteristics of the MSC8101. Junction-to-ambient Junction-to-board (bottom) Junction-to-case (top) Notes: See Section 4.1, Thermal Design Considerations, on page 4-1 for details on these characteristics. 2.5 DC Electrical Characteristics This section describes the DC ...

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Clock Configuration Core power dissipation at 300 MHz CPM power dissipation at 200 MHz SIU power dissipation at 100 MHz Core leakage power CPM leakage power SIU leakage power 2.6 Clock Configuration The following sections provide a general description of ...

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Clocks Programming Model This section describes the clock registers in detail. The registers discussed are as follows: • System Clock Control Register (SCCR) • System Clock Mode Register (SCMR) 2.6.2.1 System Clock Control Register Bit 0 TYPE RESET Bit ...

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Clock Configuration 2.6.2.2 System Clock Mode Register Bit 0 TYPE RESET 16 TYPE RESET SCMR is a read-only register that is updated during power-on reset (PORESET) and provides the mode control signals to the PLLs, DLL, and clock logic. This ...

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Table 2-8. SCMR Field Descriptions (Continued) Defaults Name Hard Bit No. PORESET Reset SPLLMF Configuration Unaffected SPLL Multiplication Factor 20–23 Pins — — — 24 DLLDIS Configuration Unaffected DLL Disable 25 Pins — — — 26–27 COREDF Configuration Unaffected Core ...

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AC Timings 2.7 AC Timings The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. AC timings are based load, except where noted otherwise, and 50 line. 2.7.1 Clocking ...

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Reset Timing The MSC8103 has several inputs to the reset logic: • Power-on reset ( • External hard reset ( • External soft reset ( Asserting an external and SRESET configuration pins: • RSTCONF • DBREQ • HPE —disable ...

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AC Timings Pin RSTCONF DBREQ/ EE0 HPE/EE1 BTM[0–1]/ EE[4–5] No. 1 Required external PORESET duration minimum • • 2 Delay from deassertion of external PORESET to deassertion of internal PORESET • • 3 Delay from deassertion of internal PORESET to ...

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Host Reset Configuration Host reset configuration allows the host to program the reset configuration word via the Host port after is deasserted, as described in the MSC8103 Reference Manual. The MSC8103 samples the PORESET signals described in Table 2-12 ...

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AC Timings Next, the MSC8103 halts until the SPLL locks. The SPLL locks according to sampled, and to MODCK_H taken from the Reset Configuration Word. SPLL locking time is 800 reference clocks, which is the clock at the output of ...

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System Bus Access Timing 2.7.3.1 Core Data Transfers Generally, all MSC8101 bus and system output signals are driven from the rising edge of the reference clock (REFCLK), which is however, trigger on four points within a REFCLK cycle. Each ...

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AC Timings No. 10 11a 11b 11c 11d 11e 11f 11g 11h 15a 15b 1 16 Notes: 2-14 Table 2-15. AC Timing for SIU Inputs Characteristic Hold time for all signals after the 50% level of the ...

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Table 2-16. AC Timing for SIU Outputs No. Characteristic 31a TA delay from the 50% level of the REFCLK rising edge • Pipeline mode • Non-pipeline mode 31b TEA delay from the 50% level of the REFCLK rising edge • ...

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AC Timings Address bus/TT[0–4]/TC[0–2]/TBST/TSIZ[0–3]/GBL inputs Address bus/TT[0–4]/TC[0–2]/TBST/TSIZ[0–3]/GBL outputs AACK/ARTRY/ABB/TS/DBG/BG/BR/DBB/CS signals 2-16 REFCLK AACK/ARTRY/TA/TEA/DBG/BG/BR PSDVAL/ABB/DBB/TS inputs Data bus inputs—normal mode Data bus inputs—ECC and parity modes DP inputs PUPMWAIT/IRQn input PSDVAL/TEA/TA outputs BADDRn Data bus outputs DP outputs Memory controller/ALE signals ...

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DMA Data Transfers Table 2-17 describes the DMA signal timing. Number The DREQ edge of REFCLK the timings in Table 2-17. Figure 2-7 shows synchronous peripheral interaction. 2.7.4 HDI16 Signals Number 44a 44b 44c ...

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AC Timings Number Notes: 2-18 Table 2-18. Host Interface (HDI16) Timing Characteristics Host data input minimum setup time before write data strobe 8 deassertion ...

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Figure 2-8 and Figure 2-9 show HDI16 read signal timing. Figure 2-10 and Figure 2-11 show HDI16 write signal timing. HA[0–3] HCS[1–2] 57 HRW HDS HD[0–15] HREQ (single host request) HRRQ (double host request) Figure 2-8. Read Timing Diagram, Single ...

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AC Timings HREQ (single host request) HRRQ (double host request) HREQ (single host request) HTRQ (double host request) 2-20 HA[0– HCS[1–2] 44a HRD HD[0–15] Figure 2-9. Read Timing Diagram, Double Data Strobe HA[0–3] 57 HCS[1–2] ...

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HA[0–3] HCS[1–2] HWR HD[0–15] HREQ (single host request) HTRQ (double host request) Figure 2-11. Write Timing Diagram, Double Data Strobe Figure 2-12 shows Host DMA read timing. HREQ (Output) HACK or HWR, HDS, HRD (Input) HD[0–15] (Output) Figure 2-12. Host ...

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AC Timings Figure 2-13 shows Host DMA write timing. 2.7.5 CPM Timings No Note: 2-22 HREQ (Output) 64 HACK or HWR, HDS, HRD (Input) HD[0–15] (Output) Figure 2-13. Host DMA Write Timing ...

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Table 2-20. CPM Output Characteristics No. Characteristic 36 FCC output delay after low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial input clock SCC/SMC/SPI/I C output delay after low-to-high clock transition a. internal clock (BRGxO) b. ...

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AC Timings Note: The timing values listed are preliminary and refer to minimum system timing requirements. Actual implementation requires conformance to the specific protocol requirements. Refer to Chapter 1 to identify the specific input and output signals associated with the ...

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JTAG Signals No. 500 501 502 503 508 509 510 511 512 513 TCK (Input) TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output) TDO (Output) Table 2-21. JTAG Timing Characteristics TCK frequency of operation TCK cycle time TCK ...

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AC Timings TCK (Input) TRST (Input) 2-26 513 512 Figure 2-22. TRST Timing Diagram ...

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Chapter 3 Packaging 3.1 Pin-Out and Package Information This sections provides information about the MSC8103 package, including diagrams of the package pinouts and tables showing how the signals discussed in Chapter 1 are allocated. The MSC8103 is available in a ...

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Lidded FC-PBGA Package Description IRQ5 D3 IRQ1 D0 B IRQ3 THERM C IRQ4 D2 DP0 1 THERM IRQ2 D EE1 EE0 2 VDDH E EE4 EE2 EE3 VDD TDO EED EE5 F TRST ...

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A D62 D63 D55 D60 BADDR B PWE6 DBG D59 D54 28 BADDR C DBB D61 D58 D53 29 D BADDR GBL PWE5 D52 D57 27 MOD PSD E PSDA D56 VDDH CK1 CAS 10 ...

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Lidded FC-PBGA Package Description 3-4 Table 3-1. MSC8103 Signal Listing By Name Signal Name A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 ...

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Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name ABB ALE ARTRY BADDR27 BADDR28 BADDR29 BADDR30 BADDR31 BCTL0 BCTL1 BG BNKSEL0 BNKSEL1 BNKSEL2 BR BRG1O BRG1O BRG2O BRG2O BRG3O BRG4O BRG5O BRG6O BRG7O BRG8O BTM0 BTM1 CD for FCC1 ...

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Lidded FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) 3-6 Signal Name Number CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 CLK9 CLK10 CLKIN CLKOUT COL for FCC1 COL for FCC2 CRS for FCC1 CRS for FCC2 CS0 CS1 ...

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Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 ...

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Lidded FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) 3-8 Signal Name Number D38 F12 D39 D12 D40 C12 D41 B12 D42 A12 D43 D13 D44 C13 D45 B13 D46 A13 D47 E14 D48 D14 D49 C14 ...

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Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name DLLIN DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 DRACK1/DONE1 DRACK2/DONE2 DREQ1 DREQ2 DREQ3 DREQ4 EE0 EE1 EE2 EE3 EE4 EE5 EED EXT_BG2 EXT_BG3 EXT_BR2 EXT_BR3 EXT_DBG2 EXT_DBG3 EXT1 EXT2 ...

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Lidded FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) 3-10 Signal Name Number GND F15 GND F5 GND F7 GND F9 GND G10 GND G12 GND G14 GND G6 GND G8 GND H15 GND H5 GND H7 ...

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Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name GND GND GND SYN GND SYN1 H8BIT HA0 HA1 HA2 HA3 HACK/HACK HCS1/HCS1 HCS2/HCS2 HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 ...

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Lidded FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) 3-12 Signal Name HREQ/HREQ HRESET HRRQ/HRRQ HRW HTRQ/HTRQ HWR/HWR INT_OUT IRQ1 IRQ1 IRQ2 IRQ2 IRQ2 IRQ3 IRQ3 IRQ3 IRQ4 IRQ5 IRQ5 IRQ6 IRQ7 IRQ7 L1RSYNC for SI1 TDMA1 ...

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Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name L1TSYNC for SI1 TDMA1 L1TSYNC for SI2 TDMB2 L1TSYNC for SI2 TDMC2 L1TSYNC for SI2 TDMD2 L1TXD for SI1 TDMA1 Serial L1TXD for SI2 TDMB2 L1TXD for SI2 TDMC2 L1TXD ...

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Lidded FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) 3-14 Signal Name Number PA8 U10 PA9 W9 PA10 U9 PA11 V8 PA12 T9 PA13 U8 PA14 W8 PA15 W3 PA16 M7 PA17 T4 PA18 W2 PA19 R5 ...

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Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name PB27 PB28 PB29 PB30 PB31 PBS0 PBS1 PBS2 PBS3 PBS4 PBS5 PBS6 PBS7 PC4 PC5 PC6 PC7 PC12 PC13 PC14 PC15 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 ...

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Lidded FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) 3-16 Signal Name Number PD17 N7 PD18 U3 PD19 V2 PD29 K2 PD30 J2 PD31 H2 PGPL0 E17 PGPL1 F14 PGPL2 G19 PGPL3 E19 PGPL4 J18 PGPL5 J17 ...

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Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name PWE2 PWE3 PWE4 PWE5 PWE6 PWE7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved RSTCONF RTS for FCC1 RTS for FCC2 RTS/TENA for SCC1 RTS/TENA for SCC2 RX_DV for FCC1 RX_DV ...

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Lidded FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) 3-18 Signal Name RXD for FCC2 transparent/HDLC serial RXD for SCC1 RXD for SCC2 RXD0 for FCC1 MII/HDLC nibble RXD0 for FCC1 UTOPIA 8 RXD0 for FCC2 MII/HDLC ...

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Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name SPICLK SPIMISO SPIMOSI SPISEL SRESET TA TBST TC0 TC1 TC2 TCK TDI TDO TEA TEST TGATE1 TGATE2 THERM1 THERM2 TIN1/TOUT2 TIN2 TIN3/TOUT4 TIN4 TMCLK TMS TOUT1 TOUT3 TRST TS TSIZ0 ...

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Lidded FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) 3-20 Signal Name TT0 TT1 TT2 TT3 TT4 TX_EN for FCC1 MII TX_EN for FCC2 MII TX_ER for FCC1 MII TX_ER for FCC2 MII TXADDR0 for FCC1 UTOPIA ...

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Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name TXD3 for FCC1 MII/HDLC nibble TXD3 for FCC1 UTOPIA 8 TXD3 for FCC2 MII/HDLC nibble TXD4 for FCC1 UTOPIA 8 TXD5 for FCC1 UTOPIA 8 TXD6 for FCC1 UTOPIA 8 ...

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Lidded FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) Table 3-2. MSC8103 Signal Listing by Pin Designator Number A10 A11 A12 A13 A14 3-22 Signal Name Number V G15 ...

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Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued) Number A15 A16 A17 A18 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 IRQ4 / DP4 / ...

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Lidded FC-PBGA Package Description Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued) Number C16 C17 C18 C19 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 ...

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Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued) Number E16 E17 E18 E19 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 G1 PA31 / FCC1:UTOPIA8:TXENB / FCC1:MII:COL G2 ...

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Lidded FC-PBGA Package Description Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued) Number G16 G17 G18 G19 H13 H14 H15 H16 H17 H18 H19 J13 ...

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Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued) Number K13 K14 K15 K16 K17 K18 K19 L1 PA27 / FCC1:UTOPIA8:RXSOC / FCC1:MII:RX_DV L2 PB28 / FCC2:RX_ER / FCC2:HDLC:RTS / SCC2:RTS/TENA / TDMB2:L1TSYNC L3 PC28 / SCC2:CTS/CLSN ...

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Lidded FC-PBGA Package Description Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued) Number M19 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 ...

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Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued) Number P16 P17 P18 P19 R1 PC22 / SI1:LIST1 / DREQ1 / CLK10 R2 R3 PA22 / FCC1:UTOPIA8:TXD3 R4 PB18 / FCC2:MII and HDLC nibble:RXD3 / I R5 PA19 / FCC1:UTOPIA8:TXD6 ...

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Lidded FC-PBGA Package Description Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued) Number T12 T13 T14 T15 T16 T17 T18 T19 U10 U11 U12 U13 U14 U15 U16 U17 U18 ...

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Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued) Number V10 PA7 / SMC2:SMSYN / TDMA1:L1TSYNC V11 V12 V13 V14 V15 V16 V17 V18 V19 W2 PA18 / FCC1:UTOPIA8:TXD7 / FCC1:MII and HDLC nibble:TXD0 / FCC1:transparent and HDLC serial:TXD W3 ...

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Lidded FC-PBGA Package Mechanical Drawing 3.3 Lidded FC-PBGA Package Mechanical Drawing Figure 3-3. MSC8103 Mechanical Information, 332-pin Lidded FC-PBGA Package 3-32 CASE 1473-01 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M–1994. 2. Dimensions in millimeters. 3. Maximum solder ball diameter ...

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Chapter 4 Design Considerations 4.1 Thermal Design Considerations The average chip-junction temperature Equation 1: T where The user should set too high, the user should either lower the ambient temperature or the power dissipation of the chip. ...

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Electrical Design Considerations 4.2 Electrical Design Considerations The input voltage must not exceed the I/O supply power-on reset. In turn, no more than 100 ms CCSYN Therefore the recommendation is to use “bootstrap” diodes between the ...

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To determine a total power dissipation in a specific application, you must add the power values derived from the above set of equations to the value derived for I/O power consumption using the following equation for each output pin: 2 ...

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Layout Practices 4.4 Layout Practices Each V CC power supply. Similarly, each power supply pins drive distinct groups of logic on the chip. The to ground using at least four 0.1 µF by-pass capacitors located as closely as possible to ...

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Index A AC timings 2-8 Address Acknowledge signal 1-10 Address Bus Busy signal 1-9 Address Bus signal 1-8 Address Latch Enable (ALE) 1-16 Address Retry signal 1-10 applications iv B block diagram i Boot Mode 0–1 (BTM[0–1]) signals 1-7 Buffer ...

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Index EOnCE Event 4 (EE4) signal 1-7 EONCE Event 5 (EE5) signal 1-7 EOnCE Event Detection (EED) signal 1-7 External Bus Grant 2 (EXT_BG2) 1-13 External Bus Grant 3 (EXT_BG3) 1-14 External Bus Request 3 (EXT_BR3) 1-13 External Data Bus ...

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FC-PBGA description 3-32 pinout bottom view 3-3 top view 3-2 PIO, timer, and DMA signal diagram 2-24 PLLs iii PORESET 1-7 power 1-4 power considerations 4-2 power consumption iii power dissipation 4-3 power-on reset flow 2-9 process technology iii product ...

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Index Host Address Line 0 (HA0) 1-10 Host Chip Select (HCS) 1-11 Host Data (H[0–15]) 1-10 Host Read Strobe (HRD) 1-11 Host Read Write Select 1-11 Interrupt Request 1 (IRQ1) 1-13 Interrupt Request 2 (IRQ2) 1-9 Interrupt Request 3 (IRQ3) ...

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Ordering Information Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability and place an order. Supply Part Voltage MSC8103 1.6 V core Lidded Flip Chip Plastic Ball Grid Array (FC-PBGA) 3.3 V I/O HOW TO REACH ...