MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 63

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

2.7.3 System Bus Access Timing
2.7.3.1 Core Data Transfers
Generally, all MSC8101 bus and system output signals are driven from the rising edge of the reference
clock (REFCLK), which is
however, trigger on four points within a REFCLK cycle. Each cycle is divided by four internal ticks: T1,
T2, T3, and T4. T1 always occurs at the rising edge of REFCLK (and T3 at the falling edge), but the
spacing of T2 and T4 depends on the PLL clock ratio selected, as Table 2-14 shows.
Figure 2-5 is a graphical representation of Table 2-14.
Note:
1:2, 1:3, 1:4, 1:5, 1:6
PLL Clock Ratio
REFCLK
REFCLK
REFCLK
The UPM machine and GPCM machine outputs change on the internal tick determined by the
memory controller programming; the AC specifications are relative to the internal tick. SDRAM
machine outputs change only on the
1:2.5
1:3.5
Figure 2-5. Internal Tick Spacing for Memory Controller Signals
T1
T1
T1
Table 2-14. Tick Spacing for Memory Controller Signals
DLLIN
T2
T2
T2
or, if the DLL is disabled,
3/10 REFCLK
4/14 REFCLK
1/4 REFCLK
Tick Spacing (T1 Occurs at the Rising Edge of REFCLK)
T2
T3
T3
T3
REFCLK
T4
T4
T4
rising edge.
CLKOUT
1/2 REFCLK
1/2 REFCLK
1/2 REFCLK
T3
. Memory controller signals,
for 1:2.5
for 1:3.5
for 1:2, 1:3, 1:4, 1:5, 1:6
11/14 REFCLK
8/10 REFCLK
3/4 REFCLK
AC Timings
T4
2-13