MSC8103M1100 Motorola / Freescale Semiconductor, MSC8103M1100 Datasheet - Page 48

• Manufacturer Part Number: MSC8103M1100
• Description: Network Processor, Networking Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

JTAG Test Access Port Signals
1.8 JTAG Test Access Port Signals
1-44
The
Standard Test Access Port and Boundary-Scan Architecture specification and described in Table 1-7.
General-
Purpose
Signal
Name
TRST
TDO
TMS
TCK
PD7
TDI
MSC8103
I/O
SMC1: SMSYN
FCC1: TXADDR3
UTOPIA master
FCC1: TXADDR3
UTOPIA slave
FCC1: TXCLAV2
UTOPIA multi-PHY master,
direct polling
supports the standard set of Test Access Port (TAP) signals defined by IEEE 1149.1
Peripheral Controller:
Output
Type
Input
Input
Input
Input
Name
Dedicated I/O
Protocol
Test Clock—A test clock signal for synchronizing JTAG test logic.
Test Data Input—A test data serial signal for test instructions and data. TDI is sampled
on the rising edge of TCK and has an internal pull-up resistor.
Test Data Output—A test data serial signal for test instructions and data. TDO can be
tri-stated. The signal is actively driven in the shift-IR and shift-DR controller states and
changes on the falling edge of TCK.
Test Mode Select—Sequences the test controller’s state machine, is sampled on the
rising edge of TCK, and has an internal pull-up resistor.
Test Reset—Asynchronously initializes the test controller, has an internal pull-up
resistor, and must be asserted after power up.
Table 1-7. JTAG Test Access Port Signals
Table 1-6. Port D Signals (Continued)
Dedicated
Direction
I/O Data
Output
Input
Input
Input
SMC1: Serial Management Synchronization
Supported by SMC1. SMSYN is an input. The SMC
interface consists of SMTXD, SMRXD, SMSYN and a clock.
Not all signals are used for all applications. SMCs are
full-duplex ports that supports three protocols or modes:
UART, transparent or general-circuit interface (GCI).
FCC1: UTOPIA Master Transmit Address Bit 3
In the ATM UTOPIA master interface supported by FCC1
using multiplexed polling, this is transmit address bit 3.
FCC1: UTOPIA Slave Transmit Cell Available 2
In the ATM UTOPIA slave interface supported by FCC1
using multiplexed polling, this is transmit address bit 3.
FCC1: UTOPIA Multi-PHY Master Transmit Cell
Available 2 Direct Polling
In the ATM UTOPIA master interface supported by FCC1
using direct polling, TXCLAV2 is asserted by an external
UTOPIA slave PHY to indicate that it can accept one
complete ATM cell.
Signal Description
Description