TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 770

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

24.2
Operation Mode
8. The 19th to 22nd bytes, transmitted from the controller the target board, indicate the start ad-
9. The 23rd and 24th bytes, transmitted from the controller to the target board, indicate the num-
10. The 25th byte is a checksum value for the 19th to 24th bytes. To calculate the checksum val-
11. The 26th byte, transmitted from the target board to the controller, is an acknowledge response
12. The 27th to mth bytes from the controller are stored in the on-chip RAM of the
13. The (m+1) th byte is a checksum value. To calculate the checksum value, add the 27th to mth
14. The (m+2) th byte is a acknowledge response to the 27th to (m+1) th bytes. First, the RAM Trans-
dress of the RAM region where subsequent data (e.g., a flash programming routine) should be
stored. The 19th byte corresponds to bits 31 to 24 of the address and the 22nd byte corre-
sponds to bits 7 to 0 of the address.
ber of bytes that will be transferred from the controller to be stored in the RAM. The 23rd
byte corresponds to bits 15 to 8 of the number of bytes to be transferred, and the 24th byte cor-
responds to bits 7 to 0 of the number of bytes.
ue, add all these bytes together, ignore the carries and caluculate the 8-bit two's complement
by using lower 8 bits then transmit this checksum value from the controller. The checksum cal-
culation is described in detail in the later Section "24.2.10.9 Checksum Calculation".
to the 19th to 25th bytes of data. First, the RAM Transfer routine checks for a receive error in
the 19th to 25th bytes. If there is a receive error, the RAM Transfer routine sends back 0x18
and returns to the command wait state (i.e., the 3rd byte) again. In this case, the upper four
bits of the acknowledge response are the same as those of the previously issued command
(i.e., 1). When the SIO4 is configured for I/O Interface mode, the RAM Transfer routine does
not check for a receive error.
Adding the series of the 19th to 24th bytes must result in 0x00 (with the carry dropped). In
case of a checksum error, the RAM Transfer routine sends back 0x11 to the controller and re-
turns to the state in which it waits for a command (i.e., the 3rd byte) again.
knowledge response (0x10) to the controller.
TMPM364F10FG. Storage begins at the address specified by the 19th to 22nd bytes and contin-
ues for the number of bytes specified by the 23rd to 24th bytes.
bytes together, ignore the carries and calculate the 8-bit two’s complement by using lower 8
bits then transmit this checksum value from the controller. The checksum calculation is descri-
bed in detail in later Section "24.2.10.9 Checksum Calculation".
fer routine checks for a receive error in the 27th to (m+1) th bytes. If there is a receive error,
the RAM Transfer routine sends back 0x18 (bit 3) and returns to the state in which it waits
for a command (i.e., the 3rd byte) again. In this case, the upper four bits of the acknowledge re-
sponse are the same as those of the previously issued command (i.e., 1). When the SIO4 is con-
figured for I/O Interface mode, the RAM Transfer routine does not check for a receive error.
Adding the series of the 27th to (m+1) th bytes must result in 0x00 (with the carry dropped).
In case of a checksum error, the RAM Transfer routine sends back 0x11 (bit 0) to the control-
ler and returns to the command wait state (i.e., the 3rd byte) again. When the above checks
have been completed successfully, the RAM Transfer routine returns a normal acknowledge re-
sponse (0x10) to the controller.
・ The 19th to 25th bytes data must be within the range of 0x2000_0400 to the end address
Next, the RAM Transfer routine performs the checksum operation to ensure data integrity.
When the above checks have been successful, the RAM Transfer routine returns a normal ac-
Next, the RAM Transfer routine performs the checksum operation to ensure data integrity.
of RAM.
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