TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 539

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TMPM364F10FG

Manufacturer Part Number
TMPM364F10FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMPM364F10FG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
Host
Can
1
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM364F10FG
Manufacturer:
Toshiba
Quantity:
10 000
Company:
Part Number:
TMPM364F10FG
Quantity:
6 000
<CECACKDIS>
CECRCR1
Transmission
Reception
(6)
imately 1.526 ms. The start time of outputting "Low" is specified with CECRCR1<CECLNC> bit
that sets the noise cancelling time.
cle error, buffer overrun and waveform error) is suspended or not. Setting "1" generates no interrupt
at the error detection.
quent bits are interrupted, it is determined as a timeout, based on the setting in <CECTOUT> of the
CECRCR1 register.
The following describes the ACK response timing.
When the falling edge of the ACK bit from the initiator is detected, this IP outputs "Low" for approx-
Configure the CECRCR1 <CECRIHLD> bit to specify if a receive error interrupt (maximum cy-
If data continues to the ACK bit, an ACK response is executed by a reversed logic. If the subse-
After the ACK response or the timeout determination, an interrupt is generated.
Note:Use <CECLNC> in the same settings used for CECTCR<CECDTRS>.
Register setting
Receive Error Interrupt Suspend
(not responding logical "0")
(responding logical "0")
(0ms to approx. 0.092ms)
"0"
"1"
<CECLNC>
0/fs - 3/fs
0.6±0.2 ms
Conformity
Yes
Page 513
Header block address
(approx.1.526ms)
50/fs
Discrepancy
No
Conformity
Yes
No
Data block address
Discrepancy
TMPM364F10FG
No
No

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