TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 623

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

17.4.1.4
17.4.1.5
17.4.1.6
RMCxRCR3 and RMCxRCR4 registers, RMC is ready for reception. Detecting a leader initiates reception.
width is shorter than a maximum low width of leader detection specified in the RMCxRCR1 <RMCLLMAX
[7:0]> bits. RMC keeps receiving data until the final data bit is received.
ta bit determination of 0 or 1 are applied regardless of whether a signal has a leader or not.
By enabling the RMCxREN <RMCREN> bit after configuring the RMCxRCR1, RMCxRCR2,
RMC stops reception by clearing the RMCxREN <RMCREN> bit to "0" (reception disabled).
Clearing this bit during reception stops reception immediately and the received data is discarded.
Setting RMCxRCR2 <RMCLD> enables RMC to receive signals with or without a leader.
By setting RMCxRCR2 <RMCLD>, RMC starts receiving data if it recognizes a signal of which low
If RMCxRCR2 <RMCLD> is enabled, the same settings of error detection, reception completion and da-
Thus receivable remote control signals are limited.
Note:Changing the configurations of the RMCxRCR1, RMCxRCR2, RMCxRCR3 and RMCxRCR4 regis-
Enabling Reception
Stopping Reception
Receiving Remote Control Signal without Leader in Waiting Leader
Waiting for leader
RMCxRCR2<RMCLD> = 1
ters during reception may harm their proper operation. Be careful if you change them during reception.
Leader waveform
Maximum data bit cycle <RMCDMAX[7:0]>
Minimum low width <RMCLLMIN[7:0]>
Maximum data bit cycle is detected if a signal stays
low shorter than specified and longer than a maximum
data bit cycle.
Page 597
RMC starts receiving data by receiving a signal which
is less than the minimum low pulse width.
TMPM364F10FG