TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 419
TMPM364F10FG
Manufacturer Part Number
TMPM364F10FG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM364F10FG.pdf
(838 pages)
Specifications of TMPM364F10FG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
Host
Can
1
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
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Table 12-9 Example of UART Mode Baud Rate (Using the Baud Rate Generator)
9.830400
fc [MHz]
The examples of baud rate in each clock settings.
・ If baud rate generator is used.
・ If the SCLK input is used
・ If fsys is used
・ If timer output is used
lowing clock settings.
verts when the value of the counter and that of TBxRG0 match. The SIOCLK clock frequen-
cy is "Setting value of TBxRG0 × 2".
Table 12-8 Clock selection in UART Mode
-
-
-
-
・ fc = 9.8304MHz
・ fgear = 9.8304MHz (CGSYSCR<GEAR[2:0]> = "000" : fc selected)
・ ΦT0 = 4.9152MHz (CGSYSCR<PRCK[2:0]> = "001" : 2 division ratio)
The highest baud rate is 1.25MHz because 20MHz is divided by 16.
Table 12-9 shows examples of baud rate when the baud rate generator is used with the fol-
To use SCLK input, the following conditions must be satisfied.
- SCLK cycle > 2/fsys
The highest baud rate must be less than 40 ÷ 2 ÷ 16 = 1.25 Mbps.
Since the highest value of fsys is 40MHz, the highest baud rate is 40 ÷ 16 = 2.5Mbps.
To enable the timer output, the following condition must be set: a timer flip-flop output in-
Baud rate can be obtained by using the following formula.
(SCxBRCR<BRS[3:0]>)
fc = 40MHz
fgear = 40MHz (CGSYSCR<GEAR[2:0]> = "000" : fc selected)
φT0 = 40MHz (CGSYSCR<PRCK[2:0]> = "000" : 1 division ratio)
Clock = φT1 = 20MHz (SCxBRCR<BRCK[1:0]> = "00" : φT1 selected)
Division ratio N
SCxMOD0<SM>
UART Mode
16
Mode
2
4
8
Page 393
76.800
38.400
19.200
9.600
(fc/4)
φT1
Baud rate generator
SCxMOD0<SC>
Clock selection
Timer output
SCLK input
19.200
(fc/16)
9.600
4.800
2.400
φT4
fsys
(fc/64)
φT16
4.800
2.400
1.200
0.600
(fc/256)
Unit : kbps
φT64
1.200
0.600
0.300
0.150
TMPM364F10FG
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