TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 630

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

18.4
Reset
18.4
18.5
18.4.1
18.4.2
(PG6) pin.
the LPSC bit of the HcRhStatus register in the OCI register to "1" makes the USBPON pin output "High" level.
USBHC sets the OCI bit in the HcRhStatus register to "1". (To use PG7 as the USBOC pin, the port G control reg-
ister (PGFR2) must be set appropriately.)
The USBHC is initialized by a hardware or software reset.
The USBHC has a control signal for the external Vbus power IC. This signal is controlled by the USBPON
To use PG6 as the USBPON pin, the port G control register (PGFR2) must be set appropriately. Then, setting
The USBOC (PG7) pin is used to detect overcurrent conditions. When low level is detected on this pin, the
Reset
Bus Power Control
up mode reset).
tus register.
A hardware reset is generated by an external reset pin or internal events (WDT reset, USBHC reset or Back-
A software reset is generated when a "1" is written to the HostControllerReset bit in the HcCommandSta-
Hardware reset
Software reset
・ All registers are initialized.
・ The reset signal is output on the bus by an external pull-down resister. (D+ = D- = 0)
・ The USB state changes to the USBRESET state.
・ List processing and SOF token generation are disabled.
・ The FrameNumber field of the HcFmNumber register is not increased.
・ All OHCI registers are initialized except the following :
・ The USBHC outputs the reset signal on the USB bus (D+ =D- =0)
・ The USB state changes to the USBSUSPEND state.
PEND state.)
-
-
(The USB transceiver is in the SUSPEND state.)
(The FunctionalState bit in the HcControl register is set to 0x03 to transition to the USBSUS-
- The RemoteWakeupConnected and InterruptRouting bits in the HcControl register remain
the same.
- The HcBCR0 register is not initialized.
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TMPM364F10FG