TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 367
TMPM364F10FG
Manufacturer Part Number
TMPM364F10FG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM364F10FG.pdf
(838 pages)
Specifications of TMPM364F10FG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
Host
Can
1
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
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11.4.7
31-3
2
1
0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
−
INTTBOF
INTTB1
INTTB0
Note 1: The factors only which is not masked by TBxIM output interrupt request to the CPU. Even if the mask setting is
Note 2: The flag is cleared by reading the TBxST register.To clear the flag, TBxST register should be read.
Bit Symbol
TBxST (Status register)
31
23
15
0
0
0
7
0
-
-
-
-
done, the flag is set.
R
R
R
R
Type
30
22
14
0
0
0
6
0
Read as "0".
Overflow flag
0:No overflow occurs
1:Overflow occurs
When an up-counter is overflow, "1" is set.
Match flag (TBxRG1)
0:No detection of a mach
1:Detects a match with TBxRG1
When a match with the timer register 1 (TBxRG1) is detected, "1" is set.
Match flag (TBxRG0)
0:No match is detected
1:Detects a match with TBxRG0
When a match with the timer register 0 (TBxRG0) is detected, "1" is set.
-
-
-
-
29
21
13
0
0
0
5
0
-
-
-
-
Page 341
28
20
12
0
0
0
4
0
-
-
-
-
27
19
11
Function
0
0
0
3
0
-
-
-
-
INTTBOF
26
18
10
0
0
0
2
0
-
-
-
INTTB1
25
17
0
0
9
0
1
0
-
-
-
TMPM364F10FG
INTTB0
24
16
0
0
8
0
0
0
-
-
-
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