TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 398

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

12.4
Registers Description
12.4.7
31-8
7
6
5
4
3
2
After reset
After reset
After reset
After reset
bit symbol
bit symbol
bit symbol
bit symbol
Bit
SCxMOD2 (Mode Control Register 2)
−
TBEMP
RBFLL
TXRUN
SBLEN
DRCHG
WBUF
Bit Symbol
TBEMP
31
23
15
0
0
0
7
1
-
-
-
R
R
R
R
R/W
R/W
R/W
Type
RBFLL
30
22
14
0
0
0
6
0
-
-
-
Read as "0".
Transmit buffer empty flag.
0: Full
1: Empty
If double buffering is disabled, this flag is insignificant.
This flag shows that the transmit double buffers are empty. When data in the transmit double buffers is
moved to the transmit shift register and the double buffers are empty, this bit is set to "1".
Writing data again to the double buffers sets this bit to "0".
Receive buffer full flag.
0: Empty
1: Full
If double buffering is disabled, this flag is insignificant.
This is a flag to show that the receive double buffers are full.
When a receive operation is completed and received data is moved from the receive shift register to the re-
ceive double buffers, this bit changes to "1" while reading this bit changes it to "0".
In transmission flag
0: Stop
1: Operate
This is a status flag to show that data transmission is in progress.
<TXRUN> and <TBEMP> bits indicate the following status.
STOP bit (For UART)
0: 1-bit
1: 2-bit
This specifies the length of transmission stop bit in the UART mode.
On the receive side, the decision is made using only a single bit regardless of the <SBLEN> setting.
Setting transfer direction
0: LSB first
1: MSB first
Specifies the direction of data transfer in the I/O interface mode.
In the UART mode, set this bit to LSB first.
Double buffer
0: Disabled
1: Enabled
This parameter enables or disables the transmit / receive double buffers to transmit (in both SCLK output /
input modes) and receive (in SCLK output mode) data in the I/O interface mode and to transmit data in
the UART mode.
When receiving data in the I/O interface mode (SCLK input) and UART mode, double buffering is enabled
in both case that "0" or "1" is set to <WBUF> bit.
<TXRUN>
1
0
TXRUN
29
21
13
0
0
0
5
0
-
-
-
Page 372
<TBEMP>
−
1
0
SBLEN
28
20
12
0
0
0
4
0
-
-
-
Transmission in progress
Transmission completed
Wait state with data in transmit buffer.
DRCHG
27
19
11
Function
0
0
0
3
0
-
-
-
Status
WBUF
26
18
10
0
0
0
2
0
-
-
-
TMPM364F10FG
25
17
0
0
9
0
1
0
-
-
-
SWRST
24
16
0
0
8
0
0
0
-
-
-