TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 671
TMPM364F10FG
Manufacturer Part Number
TMPM364F10FG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM364F10FG.pdf
(838 pages)
Specifications of TMPM364F10FG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
Host
Can
1
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
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19.5
19.5.1
19.5.2
The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR.
Control register
ry counter.
This is a register for disabling the watchdog timer function and controlling the clearing function of the bina-
Watchdog Timer Mode Register (WDMOD)
Watchdog Timer Control Register(WDCR)
1. Specifying the detection time of the watchdog timer <WDTP[2:0]>.
2. Enabling/disabling the watchdog timer <WDTE>.
3. Watchdog timer out reset connection <RESCR>
WDMOD<WDTP[2:0]> = "000".
<WDTE> bit is set to "0", and then the disable code (0xB1) must be written to WDCR register.
"1".
WDMOD<RESCR> is initialized to "1", the internal reset is generated by the overflow of binary coun-
ter.
Set the watchdog timer detecting time to WDMOD<WDTP[2:0]>. After reset, it is initialized to
When resetting, WDMOD <WDTE> is initialized to "1" and the watchdog timer is enabled.
To disable the watchdog timer to protect from the error writing by the malfunction, first
To change the status of the watchdog timer from "disable" to "enable," set the <WDTE> bit to
This register specifies whether WDTOUT is used for internal reset or interrupt. After reset,
Page 645
TMPM364F10FG
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