TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 524

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

15.3
Registers
10-8
7
6-4
3-2
1
0
Bit
CECMAX[2:0]
−
CECDAT[2:0]
CECTOUT[1:0]
CECRIHLD
CECOTH
Note 1: The settings in <CECHNC>, <CECLNC> and <CECDAT> are also used in receiving an ACK response at transmis-
Note 2: Changing the configurations during transmission or reception may harm its proper operation. Before the change,
Note 3: A broadcast message is received regardless of the <CECOTH> register setting.
Note 4: <CECLNC> must be used under the same setting as CECTCR<CECDTRS>.
Bit Symbol
sion.
set the CECREN <CECREN> bit to disable the reception and read the <CECREN> bit and the CECTEN <CEC-
TRANS> bit to ensure that the operation is stopped.
R/W
R
R/W
R/W
R/W
R/W
Type
Time to identify as maximum cycle error
Specifies the maximum time to identify as a valid bit.
Base time is 90/fs (approx.2.747 ms). Enables to specify it between the ranges −4/fs to +3/fs by the unit
of 1/fs.
An interrupt is generated when one bit cycle is longer than the specified time.
Read as 0.
Point of determining the data as 0 or 1.
Specifies the point of determining the data as logical "0" or logical "1".
Base time is 34/fs (approx.1.038 ms). Enables to specify it within ±6/fs by the unit of 2/fs.
Cycle to identify timeout
Specifies the time to determine a timeout. Enables to specify it between 1 bit and 3 bits for each bit cycle.
This setting is used to detect a timeout when the <CECRIHLD> bit is valid.
Error interrupt suspend
0: Not suspended
1: Suspended
Specifies whether to suspend a receive error interrupt (maximum cycle error, buffer overrun and waveform
error).
Setting "1" generates no interrupt at the error detection. If data continues to an ACK bit, an ACK response
is
executed by a reversed logic. If the subsequent bits are interrupted, it is determined as a timeout, based on
the setting in <CECTOUT>.
After the ACK response or the timeout determination, an interrupt is generated.
Data reception at logical address discrepancy
0: Not received
1: Received
Specifies whether to receive data when the destination address does not correspond with the address set
in the
CECADD register.
000:
001:
010:
011:
000:
001:
010:
011:
00:
01:
10:
11:
90/fs (approx. 2.747ms)
90/fs + 1/fs
90/fs + 2/fs
90/fs + 3/fs
34/fs (approx. 1.038ms)
34/fs + 2/fs
34/fs + 4/fs
34/fs + 6/fs
1 bit cycle
2 bit cycle
3 bit cycle
Reserved
Page 498
Function
100:
101:
110:
111:
100:
101:
110:
111:
90/fs − 1/fs
90/fs − 2/fs
90/fs − 3/fs
90/fs − 4/fs
34/fs − 2/fs
34/fs − 4/fs
34/fs − 6/fs
Reserved
TMPM364F10FG