TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 448
TMPM364F10FG
Manufacturer Part Number
TMPM364F10FG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM364F10FG.pdf
(838 pages)
Specifications of TMPM364F10FG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
Host
Can
1
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
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12.16
Operation in Each Mode
12.16.2
12.16.3
to "01".
(SCxCR<PE>) controls the parity enable/disable setting. When <PE> is set to "1"
odd parity may be selected using the SCxCR<EVEN> bit. The length of the stop bit can be specified using
SCxMOD2<SBLEN>.
can be added and parity enable/disable is controlled using SCxCR<PE>. If <PE> = "1" (enabled), either even
or odd parity can be selected using SCxCR<EVEN>.
The 7-bit UART mode can be selected by setting the serial mode control register (SCxMOD<SM[1:0]>)
In this mode, parity bits can be added to the transmit data stream; the serial mode control register
The following table shows the control register settings for transmitting in the following data format.
The 8-bit UART mode can be selected by setting SCxMOD0<SM[1:0]> to "10". In this mode, parity bits
The control register settings for receiving data in the following format are as follows :
Mode 1 (7-bit UART Mode)
Mode 2 (8-bit UART Mode)
Clocking condi-
tion
SCxMOD0
SCxCR
SCxBRCR
SCxBUF
x : don’t care - : no change
Clocking condi-
tion
start
start
bit 0
bit 0
←
←
←
←
System clock :
High-speed clock gear :
Prescaler clock :
System clock :
High-speed clock gear :
Prescaler clock :
1
1
7
0
x
x
*
2
2
6
0
1
0
*
3
5
1
1
3
*
-
Page 422
(Transmission rate of 9600 bps @fc = 9.8304 MHz)
4
0
0
x
*
4
4
3
0
0
x
*
High-speed (fc)
x1 (fx)
fperiph/2 (fperiph = fsys)
High-speed (fc)
x1 (fc)
fperiph/2 (fperiph = fsys)
5
5
2
1
1
x
*
6
6
1
0
0
0
*
parity
even
0
1
0
0
*
7
bps @fc = 9.8304 MHz)
parity
stop
odd
Set 7-bit UART mode
Even parity enabled
Set 2400bps
Set transmit data
stop
(enable), either even or
TMPM364F10FG
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