TMPM364F10FG Toshiba, TMPM364F10FG Datasheet - Page 17

• Manufacturer Part Number: TMPM364F10FG
• Manufacturer: Toshiba

Specifications of TMPM364F10FG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: Host
• Can: 1
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit

13. Synchronous Serial Port (SSP)
12.7 Clock Control......................................................................................................................385
12.8 Transmit / Receive Buffer and FIFO..................................................................................395
12.9 Status Flag...........................................................................................................................396
12.10 Error Flag...........................................................................................................................396
12.11 Receive..............................................................................................................................398
12.12 Transmission......................................................................................................................403
12.13 Handshake Function..........................................................................................................407
12.14 Interrupt / Error Generation Timing.................................................................................408
12.15 Software Reset...................................................................................................................410
12.16 Operation in Each Mode...................................................................................................411
13.1 Overview..............................................................................................................................425
13.2 Block Diagram.....................................................................................................................426
13.3 Register................................................................................................................................427
12.7.1
12.7.2
12.8.1
12.8.2
12.8.3
12.10.1
12.10.2
12.10.3
12.11.1
12.11.2
12.11.3
12.12.1
12.12.2
12.12.3
12.14.1
12.14.2
12.14.3
12.16.1
12.16.2
12.16.3
12.16.4
12.7.2.1
12.7.2.2
12.11.2.1
12.11.2.2
12.11.3.1
12.11.3.2
12.11.3.3
12.11.3.4
12.11.3.5
12.11.3.6
12.12.2.1
12.12.2.2
12.12.3.1
12.12.3.2
12.12.3.3
12.12.3.4
12.14.1.1
12.14.1.2
12.14.2.1
12.14.2.2
12.14.3.1
12.14.3.2
12.16.1.1
12.16.1.2
12.16.1.3
12.16.4.1
12.16.4.2
Prescaler.........................................................................................................................................................................385
Serial Clock Generation Circuit....................................................................................................................................391
Configuration.................................................................................................................................................................395
Transmit / Receive Buffer.............................................................................................................................................395
FIFO...............................................................................................................................................................................395
Mode 3 (9-bit UART Mode).......................................................................................................................................423
OERR Flag..................................................................................................................................................................396
PERR Flag...................................................................................................................................................................397
FERR Flag...................................................................................................................................................................397
Receive Counter..........................................................................................................................................................398
Receive Control Unit...................................................................................................................................................398
Receive Operation.......................................................................................................................................................398
Transmission Counter..................................................................................................................................................403
Transmission Control..................................................................................................................................................403
Transmit Operation......................................................................................................................................................404
RX Interrupt.................................................................................................................................................................408
TX interrupt.................................................................................................................................................................409
Error Generation..........................................................................................................................................................410
Mode 0 (I/O Interface Mode)......................................................................................................................................411
Mode 1 (7-bit UART Mode).......................................................................................................................................422
Mode 2 (8-bit UART Mode).......................................................................................................................................422
Baud Rate Generator
Clock Selection Circuit
I/O interface mode
UART Mode
Receive Buffer
Receive FIFO Operation
I/O interface mode with SCLK output
Read Received Data
Wake-up Function
Overrun Error
I/O interface Mode
UART Mode
Operation of Transmission Buffer
Transmit FIFO Operation
I/O interface Mode/Transmission by SCLK Output
Underrun Error
Single Buffer / Double Buffer
FIFO
Single Buffer / Double Buffer
FIFO
UART Mode
I/O Interface Mode
Transmitting Data
Receive
Transmit and Receive (Full duplex)
Wake-up Function
Protocol
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