SI5040-D-GM Silicon Laboratories Inc, SI5040-D-GM Datasheet - Page 96

• Manufacturer Part Number: SI5040-D-GM
• Description: IC TXRX XFP 10GBPS 32LGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5040-D-GM

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si5040
14. Pin Descriptions: Si5040
96
*Note: TYPE: P = Power; AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Output; DIO = Digital
19,18
13,14
Pin
7, 6
16
Input/Output.
INTERRUPT
REFCLK+
REFCLK–
RXDIN+
RXDIN–
Name
RD+
RD–
Figure 24. Si5040 Pin Configuration (Transparent Top View)
Type*
DO
AO
AI
AI
Differential CML Receiver Data Output.
Differential CML Receiver Data Input.
or Open Drain
Table 13. Si5040 Pin Descriptions
LVTTL
Level
PECL
RX_LOS
RX_LOL
RXDIN–
RXDIN+
VDDIO
GND
GND
GND
1
2
3
4
5
6
7
8
32
9
31
10
Interrupt (Active Low).
The interrupt output pin is provided to indicate potential fault
conditions or changes in status. Interrupt sources are mask-
able by setting the Interrupt Mask register, and interrupt status
is available from the Interrupt Status register. The interrupt
function can be disabled in the Interrupt Enable bit. The inter-
rupt pin can be configured via the Interrupt Output register as
either an open drain output (default) or LVTTL output.
High-speed XFI-compliant receiver data output recovered
from the RXDIN input.
Reference Clock Input.
A reference clock at this input is applied to the transmit CMU
and to the receiver and transmitter CDRs. The use of a refer-
ence clock is optional.
If the jitter performance of the external reference clock is
acceptable, the Si5040 can be operated in CMU mode. In this
mode, the CMU derives the line-rate clock by multiplying the
clock frequency applied to the REFCLK inputs. If the REFCLK
input is synchronous, the CMU multiplies the frequency by 64.
The resulting line-rate is frequency-locked to the serial data. A
FIFO in the data path accommodates any jitter differences
between the serial data and the CMU line-rate clock.
Data signal RD is recovered from the high-speed differential
signal present on these pins.
Data over the 9.95 Gbps to 11.3 Gbps range is recovered.
Rev. 0.86
GND
GND
PAD
PAD
11
30
29
12
28
13
GND
PAD
GND
PAD
27
14
26
15
25
16
24
23
22
21
20
19
18
17
SCK
GND
TD+
TD–
GND
RD+
RD–
GND
Description