SI5040-D-GM Silicon Laboratories Inc, SI5040-D-GM Datasheet
SI5040-D-GM
Specifications of SI5040-D-GM
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SI5040-D-GM Summary of contents
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... The device supports referenceless operation or operation with a synchronous or asynchronous reference clock. The device can be completely configured through a serial microcontroller interface. The Si5040 is compliant with all XFP requirements in both datacom and telecom applications. The Si5040 is packaged in a 5x5 mm LGA package and dissipates 575 mW (typ). Functional Block Diagram ...
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... Si5040 2 Rev. 0.86 ...
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... T C ABLE O F ONTENTS Section 1. Si5040 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5. Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1. Receive Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2. Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5.3. Receive Amplitude Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4. Receiver Loss of Signal Alarm (LOS 5.5. Receiver Slice Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 ...
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... Si5040 1. Si5040 Detailed Block Diagram 4 Rev. 0.86 ...
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... DDIO > 1.62 V should be less than 50 ms. Any ramp-up time slower than ISE ISE Figure 1. Voltage Measurement t F Rev. 0.86 Si5040 1 Typ 1 Unit Min Max C – 1.62 1.80 1.89 V 1.62 — 3.63 V Single-Ended OSE Peak-to-Peak Voltage Differential Peak-to-Peak Voltage t 80% 20% ...
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... Si5040 Table 2. DC Characteristics (V = 1.8 V +5%/–10 – ° Parameter Supply Current Power Dissipation Differential Input Voltage Swing (RXDIN) –12 (at BER 10 ) Common Mode Output Voltage (TXDOUT) Differential Output Voltage Swing (TXDOUT), Differential Peak-to-Peak OutLevel[2:0] = 111 110 101 100 011 010 001 ...
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... IHI2C V DDIO 0 –10 II2C IN DDIO to 0 DDIO 1.8 V 0.1 x HYSI2C DDIO 3.3 V 0.05 x DDIO 1.8 V — OLI2C DDIO 3.3 V — DDIO Rev. 0.86 Si5040 Typ Max Unit — 0 DDIO — — V — 10 µA — — V — — V — 0 — 0 PPD 7 ...
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... Si5040 Table 3. AC Characteristics–RXDIN (Receiver Input) = – 1.8 V +5/–10 Parameter Rx Path Data Rate Input Return Loss (RXDIN) ALOS Range ALOS Step Size ALOS Relative Accuracy DLOS Range DLOS Accuracy ALOS Hysteresis (Programmable 0.4 dB steps) Slice Voltage Range Slice Voltage Error ...
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... GHz DJ >4 MHz. See Appendix E1 in the XFP specification See Figure 3. X2 See Figure 3. Y1 See Figure 3. Y2 See Figure 3. J 9.95 Gbps BW 10 Rev. 0.86 Si5040 Min Typ Max — — — — 20 — — 8 — — * — ...
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... Si5040 –Y1 –Y2 0.0 X1 Figure 3. Receiver Differential Output Mask (RD 1–X2 1–X1 Normalized Time (UI) Rev. 0.86 1.0 ...
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... GHz 10 GHz–16 GHz OC-192, CMU mode 0 J GEN(rms) OC-192, CMU mode 0 J GEN(PP) J 9.95 Gbps BW < 120 kHz FREQ RC DUTY RC TOL Rev. 0.86 Si5040 Min Typ Max Unit — — — — dB mUI RMS — 2.8 4.6 — ...
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... Si5040 Table 6. CMU Timing Modes Mode Description 0 No Reference Clock or Asynchronous Reference Clock 3 1 Clean, synchronous 1,3 2 Clean, asynchronous Notes: 1. Reference clock with frequency equal to Baud rate /64 ±100 ppm and phase noise as defined in XFP Specification 3.1, Section 3.9. 2. Since the default bandwidth for this mode is 100 kHz, Register 134 [7:4] should be written to a “4” to set the bandwidth to 380 kHz ...
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... Si5040 TD Jitter Tolerance (Typ) 100 10 1 0.1 0. 100 Figure 4. XFI Sinusoidal Jitter Tolerance ( –Y1 –Y2 0.0 X1 Figure 5. Transmitter Differential Input Mask (TD) 1000 10000 100000 1000000 Frequency (Hz) PP 1–X1 Normalized Time (UI) Rev. 0.86 Si5040 XFI Specification 10000000 100000000 ) 1.0 13 ...
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... Si5040 2 Table 8. AC Characteristics—I = – 1.8 V +5/–10 Parameter Symbol Pin capacitance C II2C Table 9. Switching Characteristics—Serial Microcontroller Interface V = 1.8 V +5/–10 3.3 V ±10 DDIO Parameter Cycle Time SCK Rise Time, SCK Fall Time, SCK Low Time, SCK High Time, SCK ...
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... SCK t lsc t su1 Figure 6. Serial Microcontroller Interface Timing Diagram SS SCK Figure 7. SPI-Like Interface Write/Set Address Command SS SCK Read Command Figure 8. SPI-Like Interface Read Command hsc t t su2 Rev. 0.86 Si5040 Read Data 15 ...
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... Si5040 Table 10. Absolute Maximum Ratings* Parameter DC Supply Voltage LVTTL Supply Voltage Differential Input Voltages Maximum Current any Output PIN Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pf, 1.5 k) *Note: Permanent device damage can occur if the absolute maximum ratings are exceeded. Restrict functional operation to the conditions specified in the operational sections of this data sheet ...
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... Typical Application Schematic TXDOUT- TXDOUT+ VDDIO .1 UF RXDIN RXDIN VDD_1P8 VDD_1P8 . GND1 2 RX_LOL 3 RX_LOS 4 SI5040 VDDIO 5 U? GND2 6 RXDIN- 7 RXDIN+ 8 GND3 VDD_1P8 REFCLK+ REFCLK- Rev. 0.86 Si5040 VDD_1P8 SCK TD+ 23 GND4 . TD+ TD- 21 TD- 20 GND5 19 RD RD- RD- 17 GND6 .1 UF RD+ VDD_1P8 17 ...
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... XFP transceiver bidirectional signal conditioner for use in XFP modules as defined by the XFP multi-source agreement. The Si5040 includes independent clock and data recovery units (CDRs) and frequency-agile, jitter-attenuating clock multiplier units (CMUs) in both receive and transmit directions. The receive path includes a limiting ...
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... Receiver Loss of Signal Alarm (LOS) The Si5040 receiver generates a loss-of-signal alarm when the input signal fails to meet the selected programmable condition for loss of signal. The programmable LOS mode is controlled in the RxlosCtrl register (Register 10) ...
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... Si5040 Is Count > dLosClearThresh *16 +1 The receiver may be programmed to perform any of the following consequent actions upon declaring RX_LOS: 1. Lock the receiver to the applied reference clock (lock to reference): ltrOnLOS bit in Register 7. 2. Assert receiver loss of lock (LOL): lolOnLOS bit in Register 7. 3. Disable (squelch) the receive data output (RD): SquelchOnRxLOS bit in Register 28. ...
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... The internal VCO pull range will be automatically re- centered to the reference clock frequency to start the CDR lock acquisition process. Note that LOL will not be cleared. Rev. 0.86 Si5040 LOLonLOS = 1 and ltrOnLos = 1? Next Figure VCOCAL[1: VCOCAL[1:0] = 11? (Default refClk ...
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... Autoslice and constant duty cycle are the preferred slice modes of operation for Telecom and Datacom applications. 5.6. Clock and Data Recovery (CDR) The Si5040 integrates a CDR to recover the clock and data from the input signal applied to RXDIN. The CDR can be operated with or without an external reference clock. ...
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... In addition, for proper LOL performance, RxPDGainAcq (Register 77) must be written once to 0Dh after power is applied reset is implemented. 5.8.2. Frequency LOL The Si5040 supports the use of a ~622 MHz or ~155 MHz (/64 or /16) reference clock. The reference clock frequency is selected in the ChipConfig1 register (Register 2). When FREQLOL is set (Register ...
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... Si5040 aLOSThresh (Bit 1:0, Register 13 and Bit 7:0, Register 12) aLOSHyst[3:0] (Bit 7:4, Register 13) Peak-to- Peak Monitor RxdLosAssertThresh[7:0] (Bit 7:0, Register 17) RxdLosClearThresh (Bit 7:0, Register 18) DLOS Monitor EN dLosEn[1:0] (Bit 2:1, Register 10) 00: Disabled (Default) 01: Based on consecutive number of 1s 01: Based on consecutive number of 0s ...
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... Register 56 controls the RD signal amplitude. The resistors and capacitors can be generic exceed the jitter low-cost components, and the circuit should be located very close to the Si5040 RD± pins. This circuit is recommended for all XFP applications. Rev. 0.86 Si5040 LOS (Bit 5, Register 137 or ...
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... Si5040 5040 5040 274 274 Figure 17. RD Pre-Emphasis Circuit Rev. 0. µ ...
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... XFI channel and the equalizer should be essentially flat. 6.3. Clock and Data Recovery (CDR) The Si5040 integrates a CDR to recover the clock and data from the signal applied to the TD input. The CDR may be operated with or without an external reference clock. Reference and referenceless operation is programmed in the TxCalConfig register (Register 136) ...
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... Si5040 6.4.2. Frequency LOL The Si5040 supports the use of a ~622 MHz or ~155 MHz (/64 or /16) reference FREQLOL is set (Register 135[3:2] = 10b), LOL is asserted if the recovered clock frequency deviates from the reference clock frequency by ±1000 ppm. LOL is de- asserted if the recovered clock is within ±200 ppm of the ...
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... XFI Recovered Clock CDR FIFO XFI Recovered Data ® DSPLL Jitter Attenuator CMU Phase XFI Recovered in Clock FIFO CDR XFI Recovered Data Figure 20. Mode 2 Rev. 0.86 Si5040 CDR Equalizer TD Synchronous Reference Clock Equalizer TD Asynch Ref Clock (Mode 2) Phase out Equalizer TD 29 ...
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... Loopback Modes The Si5040 supports XFI Loopback, Lineside Loopback, and Looptime modes. 7.1. XFI Loopback The Si5040 is configured in the XFI Loopback mode by writing to the ChipConfig1 register (Register 2). The Si5040 is configured in the XFI Loopback mode by writing to the ChipConfig1 register (Register 2). Data on the TD input is retimed and output on the RD output. ...
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... I C Interface When configured in I low), the control interface to the Si5040 is a 2-wire bus for bidirectional communication. The bus consists of a bidirectional serial data line (SD) and a serial clock input receiver pattern (SCK). The SD pin may be configured as a CMOS output open drain output using Register 2, bit 4 ...
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... MSB first. The SD is high- commonly-available impedance on the rising edge of SS. During write operations, data is driven into the Si5040 via the SD pin MSB first. Data always transitions with the falling edge of the clock and is latched on the rising edge. ...
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... Interrupt Status bit to set. All of the Interrupt Status bits are logically “NORed” together to create the Interrupt bit (or pin16). Please refer to Figure 23 for an illustration of the device interrupt tree. The polarity of the Interrupt (pin 16) is active low. Rev. 0.86 Si5040 33 ...
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... Si5040 RX_REFLOS Q D Alarm status bit (Register 9, bit 6) CK RX_REFLOS C Interrupt mask bit 10 MHz Clock (Register 4, bit 6) Clear Interrupt Enable (Register 2, bit 5) RX_LOS Q D Alarm status bit (Register 9, bit RX_LOS 10 MHz Clock Write-to-Clear Interrupt mask bit (Register 4, bit 5) Clear Interrupt Enable ...
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... If SPSEL is low (I C mode), power up from both sides powered down can only be accomplished by physically removing VDD from the Si5040 and then re-applying VDD. Of course, this will power up both sides of the device, and a hard recal will automatically occur. Note that interrupts must be masked or ignored during power down and unmasked and cleared after the recalibration ...
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... Si5040 13. Si5040 Register Summary Any reserved bits listed in the table below or reserved registers (23, 54–55, 58–76, 78–83, 86–97, 99–105, 110– 130, 140–144, 148–151, 182–183, 185–204, 206–225, and 227–255) must not be written to a non-default value. ...
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... RxtpArbChkPtn[47:40] RxtpArbChkPtn[55:48] RxtpArbChkPtn[63:56] RxtpChkErrCnt[23:16] RxtpChkErrCnt[31:24] RxtpChkErrCnt[39:32] HsPowerCtl[1:0] Reserved Reserved RxPDGainAcq[2:0] Reserved RxEqGain RxEqHFBoost Reserved Reserved Reserved Reserved Reserved Reserved Rev. 0.86 Si5040 Bit 4 Bit 3 Bit 2 Reserved tpSyncMask RxtpArbGenPtn[7:0] RxtpArbChkPtn[7:0] RxtpArbChkPtn[15:8] RxtpTargetErr[7:0] RxtpChkErrCnt[7:0] RxtpChkErrCnt[15:8] RxtpChkErr[7:0] Reserved outLevel[2:0] Reserved Reserved Reserved Reserved RxLoopFAcq[6:0] ...
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... Si5040 Reg Name Default 131 TxChipConfig2 22h Reserved 132 TxintMask 0h Reserved 133 TxintStatus 0h Reserved (Sticky Bits) 134 TxCmuConfig 40h 135 TxConfig 94h Reserved 136 TxCalConfig 0h Reserved 137 TxAlarmStatus 0h Reserved 138 TxLosCtrl Eh Reserved 139 TxLosStatus 0h Reserved 145 TxdLosAssert- 00 Thresh 146 TxdLos 60h ...
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... TxPDGainAcq 8Dh 226 TxLoopFAcq 1Eh TxLoop FAcqCtl Bit 7 Bit 6 Bit 5 TxtpArbChkPtn[47:40] TxtpArbChkPtn[55:48] TxtpArbChkPtn[63:56] TxtpChkErrCnt[23:16] TxtpChkErrCnt[31:24] TxtpChkErrCnt[39:32] HsPowerCtl[1:0] Reserved Reserved TxPDGainAcq[2:0] Reserved Rev. 0.86 Si5040 Bit 4 Bit 3 Bit 2 TxtpTargetErr[7:0] TxtpChkErrCnt[7:0] TxtpChkErrCnt[15:8] TxtpChkErr[7:0] Reserved outLevel[2:0] Reserved Reserved Reserved TxLoopFAcq[6:0] Bit 1 Bit 0 Reserved 39 ...
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... Si5040 Register 0. Part Identifier Bit D7 D6 Name Type Reset settings = 0100 0000 Bit Name 7:0 Identifier[7:0] Second and least significant digit of the device part number (40). Register 1. Part Identifier Bit D7 D6 Name Revision[3:0] Type Reset settings = 0011 0000 Bit Name 7:4 Revision[3:0] Die revision (Revision decimal) ...
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... Normal operation Optical data loopback. 1 XFILoopback XFI Loopback Mode Control Normal operation XFI loopback. 0 refClkFreq Reference Clock Frequency Select 155 MHz 622 MHz intEnable spiOpenDrain Reserved R/W R/W R/W Function Rev. 0.86 Si5040 lineside XFI refClkFreq Loopback Loopback R/W R/W R/W 41 ...
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... Si5040 Register 3. RxChipConfig2 Bit D7 D6 Name Type R R Reset settings = 0000 0000 Bit Name 7:1 Reserved Read returns zero. 0 RxPdn Receiver Power Down Normal operation Receiver powered down. A hard recal must be performed to calibrate all circuits (Rx hardRecal at Register 8, Bit 3) when the receiver is returned to normal operation after a power down. ...
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... Signal Quality Monitor Alarm Interrupt Unmasked. sqmAlarm generates an alarm on the Interrupt output (pin 16) if inter- rupts are enabled. (intEnable = sqmAlarm is ignored LOS LOL fifoErr tpErrAlarm tpSyncLos R/W R/W R/W Function Rev. 0.86 Si5040 sqmAlarm R/W R/W R/W 43 ...
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... Si5040 Register 5. RxintStatus (Sticky Bits) Bit D7 D6 Name refLOS Type R R/W Reset settings = 0000 0000 Bit Name 7 Reserved Read returns zero. 6 refLOS Reference Clock LOS Interrupt. A latched version of the refLOS alarm status bit. An interrupt is generated if interrupts are enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The interrupt may be cleared by writing a zero to this bit position or by disabling interrupts ...
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... Not supported 0001 = Not supported 0010 = Not supported 0011 = Not supported 0100 = 380 kHz Default 0101 = Not supported 0110 = Not supported 3 Reserved Read returns zero. 2:0 Reserved Do not change; must only write 000 to these bits Function Rev. 0.86 Si5040 Reserved R/W 45 ...
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... Si5040 Register 7. RxConfig Bit D7 D6 Name lolOnLOS ltrOnLOS Type R R/W Reset settings = 0001 0101 Bit Name 7 Reserved Read returns zero. 6 lolOnLOS Loss of Lock on Loss of Signal Normal LOL operation Assert loss of lock on a loss of signal condition. 5 ltrOnLOS Lock to Reference on Loss of Signal Normal LTR operation. ...
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... Invalid mode. Note that receive LOL will always be on. Note: VCOCAL[1:0] must be set to reference (10b) or auto mode (00b) when part is configured XFI loopback mode. 0 swReset Reset Normal operation Reset all registers. Bit is cleared upon completion of reset hardRecal R R R/W Function Rev. 0.86 Si5040 VCOCAL[1:0] swReset R/W R/W R/W 47 ...
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... Si5040 Register 9. RxAlarmStatus Bit D7 D6 Name refLOS Type R R Reset settings = 0000 0000 Bit Name 7 Reserved Read returns zero. 6 refLOS Reference Clock LOS Alarm. Loss of signal on the reference clock input, based on a coarse deviation in frequency. 5 LOS Loss of Signal Alarm. Loss of signal on the receiver input. ...
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... Digital LOS alarm is based on the consecutive number of ones programmed in Reg- ister 17 Digital LOS alarm is based on the consecutive number of either zeros or ones pro- grammed in Register 17. 0 aLosEn Analog LOS Enable Disabled Analog LOS alarm active sqmLosEn R R R/W Function Rev. 0.86 Si5040 dLosEn[1:0] aLosEn R/W R/W 49 ...
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... Si5040 Register 11. RxLosStatus Bit D7 D6 Name Type R R Reset settings = 0000 0000 Bit Name 7:5 Reserved Read returns zero. 4 sqmLOS Signal Quality Monitor LOS. When the internal signal quality monitor (Reg25) is less than the threshold in registers 26 and 27, this bit will be high LOL (Reg9[4]) is high, this bit is forced ...
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... Reset settings = 0000 0000 Bit Name 7:0 peakDet[7:0] Peak Detector Signal Amplitude. Least significant byte of the receiver peak detector signal amplitude in mV. This register should be read before register 16 Reserved R Function value = (aLosHyst + 16)/16 * aLosThresh in mVppd peakDet[7:0] R Function Rev. 0.86 Si5040 aLosThresh[9:8] R ...
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... Si5040 Register 16. peakDet Bit D7 D6 Name Type Reset settings = 0000 0000 Bit Name 7:2 Reserved Read returns zero. 1:0 peakDet[9:8] Peak Detector Signal Amplitude. Most significant two bits of the receiver peak detector signal amplitude in mV. This regis- ter should be read after reading Register 15. ...
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... Do not change; must only write 0001 to these bits. 3 Reserved Read returns zero. 2:0 sliceEn[2:0] Slice Mode Enable. 000 = Slice disabled. 001 = Autoslice enabled. 010 = Constant duty cycle slice enabled. 011 = Proportional slice enabled. 100 = Absolute slice mode enabled RxdLosClearThresh[7:0] R/W Function Function Rev. 0.86 Si5040 sliceEn[2:0] R/W 53 ...
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... Si5040 Register 21. sliceLvl Bit D7 D6 Name Type Reset settings = 0000 0000 Bit Name 7:0 sliceLvl[7:0] Slice Level. Least significant byte of slice level setting. 2's compliment signed value. Absolute mode: Proportional Mode: Constant Duty Cycle Mode: Register 22. sliceLvl Bit D15 D14 Name ...
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... Name Type R Reset settings = undefined Bit Name 7:6 Reserved Read returns zero. 5:0 RxSqmValue[5:0] Receiver Signal Quality Monitor Value. Measured value of the magnitude of the received signal's horizontal eye opening. 00 0000 = minimum 11 1111 = maximum RxphaseAdjust[6:0] R/W Function RxSqmValue[5:0] R Function Rev. 0.86 Si5040 ...
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... Si5040 Register 26. RxSqmConfig Bit D7 D6 Name Type Reset settings = 0010 1001 Bit Name 7:2 RxSqmThresh[5:0] Receiver Signal Quality Monitor Threshold. Threshold used to assert SQM LOS alarm. 00 0000 = 0 (decimal) 11 1111 = 63 (decimal) Note: Default = 10 (decimal) 1 Reserved Do not change; must only write 0 to this bit. ...
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... RXintMask register (Reg4[1]). FIFO pointer is reset to center value and FIFO is cleared. 0 FIFOReset FIFO Reset Normal operation Reset receive FIFO. FIFO pointer is reset to center value and FIFO is cleared clkOnLOS SquelchOn SquelchOn RxLOL RxLOS R/W R/W R/W Function Rev. 0.86 Si5040 Squelch FIFOAuto FIFOReset Reset R/W R/W R/W 57 ...
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... Si5040 Register 29. RxtpSel Bit D7 D6 Name tpChkInvert Type R/W Reset settings = 0000 0000 Bit Name 7 tpChkInvert Test Pattern Checker Data Invert Normal operation Invert data applied to test pattern checker. 6:4 tpChkSel[2:0] Test Pattern Checker Mode Select. 000 = Pattern checker disabled. 001 = Check for PRBS7 pattern. ...
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... RxtpArbGenPtn[7:0] Receiver Test Pattern Generator User Defined Pattern. Note: Bit 0 in Register 31 is the LSB of the 64-bit user-defined pattern, and Bit 7 in Register tpSyncMask R R/W Function RxtpArbGenPtn[7:0] R/W Function 38 is the MSB. The transmit sequence is from LSB to MSB. Rev. 0.86 Si5040 tpTimeBase[1:0] R ...
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... Si5040 Register 32. RxtpArbGenPtn Bit D15 D14 Name Type Reset settings = 1010 1010 Bit Name 7:0 RxtpArbGenPtn[15:8] Receiver Test Pattern Generator User Defined Pattern. Note: Bit 0 in Register 31 is the LSB of the 64-bit user-defined pattern, and Bit 7 in Register Register 33. RxtpArbGenPtn Bit ...
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... RxtpArbGenPtn[47:40] R/W Function Register 38 is the MSB. The transmit sequence is from LSB to MSB. D53 D52 D51 RxtpArbGenPtn[55:48] R/W Function Register 38 is the MSB. The transmit sequence is from LSB to MSB. Rev. 0.86 Si5040 D34 D33 D32 D42 D41 D40 D50 D49 D48 61 ...
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... Si5040 Register 38. RxtpArbGenPtn Bit D63 D62 Name Type Reset settings = 1010 1010 Bit Name 7:0 RxtpArbGenPtn[63:56] Receiver Test Pattern Generator User Defined Pattern. Note: Bit 0 in Register 31 is the LSB of the 64-bit user-defined pattern, and Bit 7 in Register 39. RxtpArbChkPtn Bit D7 D6 ...
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... RxtpArbChkPtn[31:24] R/W Function Register 46 is the MSB. The receive sequence is from LSB to MSB. D37 D36 D35 RxtpArbChkPtn[39:32] R/W Function Register 46 is the MSB. The receive sequence is from LSB to MSB. Rev. 0.86 Si5040 D18 D17 D16 D26 D25 D24 D34 D33 D32 63 ...
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... Si5040 Register 44. RxtpArbChkPtn Bit D47 D46 Name Type Reset settings = 1010 1010 Bit Name 7:0 RxtpArbChkPtn[47:40] Receiver Test Pattern Checker User Defined Pattern. Note: Bit 0 in Register 39 is the LSB of the received 64-bit user-defined pattern, and Bit 7 Register 45. RxtpArbChkPtn Bit D55 ...
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... When using a defined timebase, this register holds the error count from the last com- pleted timebase. In the continuous timebase setting, the register holds the current running error count. Reading the least significant byte (LSB) latches the upper bytes RxtpTargetErr[7:0] R/W Function Exponent 15 (decimal RxtpChkErrCnt[7:0] R Function Rev. 0.86 Si5040 ...
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... Si5040 Register 49. RxtpChkErrCnt (40-bit Register) Bit D15 D14 Name Type Reset settings = undefined Bit Name 7:0 RxtpChkErrCnt[15:8] Receiver Test Pattern Checker Error Count. When using a defined timebase, this register holds the error count from the last completed timebase. In the continuous timebase setting, the register holds the cur- rent running error count ...
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... Measured error count in 8-bit floating point notation. The contents of this register are an alternative format to the RxtpChkErrCnt. Mantissa = bits [7:4] Exponent = bits [3:0] Error count = (Mantissa/16 0000 0000 = 0 (decimal) 1111 1111 = (15/16 D37 D36 D35 RxtpChkErrCnt[39:32] R Function 0000000000 = 0 (decimal) 40 FFFFFFFFFF = 2 – 1 (decimal RxtpChkErr[7:0] R Function Exponent 15 (decimal) Rev. 0.86 Si5040 D34 D33 D32 ...
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... Si5040 Register 56. OutputLevel Bit D7 D6 Name Reserved Type R/W Reset settings = 1111 0101 Bit Name 7:6 Reserved Do not change; must only write 11 to these bits. 5:3 Reserved These bits are not user defined, and writes to these bits are ignored. 2:0 outLevel[2:0] RD output drive level ...
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... Reserved Do not change; must only write 00000 to these bits Function 0 dB (max gain) –2 dB –2 dB (same as 001 setting) –3 dB –4 dB –5 dB –6 dB –7 dB (min gain Function 0 dB (min boost setting (max boost setting) Rev. 0.86 Si5040 Reserved R Reserved R/W 69 ...
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... Si5040 Register 98. RxLoopFAcq Bit D7 Name RxLoopFAcqCtl Type R/W Reset settings = 0001 1110 Bit Name 7 RxLoopFAcqCtl Rx Acquistion Loop Filter Override Use value written in Bit [6:0]. Set to 1 only when Rx LOL is asserted Use internally generated value. Set to 0 when Rx LOL is deasserted. 6:0 RxLoopFAcq[6:0] Rx Loop Filter Setting for Acquisition ...
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... Bit [8:1] of sqmLOL Threshold setting; value is unsigned integer value. RxLOL is asserted when jitter measure exceeds value in sqmLOLThresh[13:0] and is deasserted when jitter measure is below the threshold. Refer to Section 5.8.1 for more information about this register Reserved R/W Function sqmLOLThresh[8:1] R/W Function Rev. 0.86 Si5040 ...
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... Si5040 Register 109. sqmLOLThresh Bit D7 D6 Name Reserved Type R/W Reset settings = 0000 0000 Bit Name 7:5 Reserved Reserved. Should be written to 101b. 4:0 sqmLOLThresh[13:9] SQM LOL Threshold. Bit [13:9] of sqmLOL Threshold setting; value is unsigned integer value. RxLOL is asserted when jitter measure exceeds value in sqmLOLThresh[13:0] and is deasserted when jitter measure is below the threshold ...
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... Signal Quality Monitor Alarm Interrupt Unmasked. sqmAlarm generates an alarm on the Interrupt output pin (pin 12) if inter- rupts are enabled. (intEnable = 1 sqmAlarm is ignored LOS LOL fifoErr tpErrAlarm tpSyncLos R/W R/W R/W Function Rev. 0.86 Si5040 sqmAlarm R/W R/W R/W 73 ...
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... Si5040 Register 133. TxintStatus (Sticky Bits) Bit D7 D6 Name refLOS Type R R/W Reset settings = 0000 0000 Bit Name 7 Reserved Read returns zero. 6 refLOS Reference Clock LOS Interrupt. A latched version of the refLOS alarm status bit. An interrupt is generated if interrupts are enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The interrupt may be cleared by writing a zero to this bit position or by disabling interrupts ...
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... Looptime Mode with Clean Reference Clock. (Recommended CMU bandwidth = 1.37 kHz.) Note: An automatic recalibration is executed after a change in timing mode Function Valid for CMU modes only. Valid for CMU modes only. Valid for CMU modes 0 and 1 only. Rev. 0.86 Si5040 cmuMode[2:0] R/W 75 ...
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... Si5040 Register 135. TxConfig Bit D7 D6 Name Type Reset settings = 1001 0100 Bit Name 7:5 Reserved Do not change; must only write 100 to these bits. 4 CDRLTDATA CDR Lock Acquisition Options when Lock to Reference is Enabled CDR phase locks to reference clock CDR continues to attempt to lock to data. ...
Page 77
... Invalid mode. Note that transmit LOL will always be on. Note: VCOCAL[1:0] must be set to reference(10b) or auto mode (00b) when part is configured Lineside loopback mode. 0 swReset Software Reset Normal operation Reset. Bit is cleared upon completion of reset hardRecal R R R/W Function Rev. 0.86 Si5040 VCOCAL[1:0] swReset R/W R/W R/W 77 ...
Page 78
... Si5040 Register 137. TxAlarmStatus Bit D7 D6 Name refLOS Type R R Reset settings = 0000 0000 Bit Name 7 Reserved Read returns zero. 6 refLOS Reference Clock LOS Alarm. Loss of signal on the reference clock input, based on a coarse deviation in frequency. 5 LOS Loss of Signal Alarm. Loss of signal on the transmitter input. (TD) ...
Page 79
... Holds a zero or one depending on which bit caused the last digital LOS event. 2 dLOS Digital Loss of Signal. Digital LOS event status bit. 1 Reserved Read returns zero. 0 LOS Loss of Signal. LOS status bit sqmLosEn R R/W Function sqmLOS dLOSlastTrigger Function Rev. 0.86 Si5040 dLosEn[1:0] R dLOS LOS ...
Page 80
... Si5040 Register 145. TxdLosAssertThresh Bit D7 D6 Name Type Reset settings = 0000 0000 Bit Name 7:0 TxdLosAssertThresh Transmitter Digital Loss of Signal Assert Threshold. The number of consecutive identical digits before digital LOS is asserted. Assert threshold in bits = (TxdLosAssertThresh 1024. See Figure 10 on page 19. ...
Page 81
... Reset settings = 0000 0000 Bit Name 7:6 Reserved Read returns zero. 5:0 TxSqmValue[5:0] Transmitter Signal Quality Monitor Value. Measured value of the magnitude of the transmitter's received signal horizontal eye opening. 00 0000 = minimum 11 1111 = maximum TxphaseAdjust[6:0] R/W Function TxSqmValue[5:0] R/W Function Rev. 0.86 Si5040 ...
Page 82
... Si5040 Register 154. TxSqmConfig Bit D7 D6 Name Type Reset settings = 0000 0101 Bit Name 7:2 TxSqmThresh[5:0] Transmitter Signal Quality Monitor Threshold. Threshold used to assert SQM LOS alarm. 00 0000 = 0 (decimal) 11 1111 = 63 (decimal) Note: Default = 1 (decimal) 1 Reserved Do not change; must only write this bit. ...
Page 83
... FIFO on FIFO underflow or overflow. FIFO pointer is reset to center value and FIFO is cleared. 0 FIFOReset FIFO Reset Normal operation reset transmit FIFO. FIFO pointer is reset to center value and FIFO is cleared SquelchOnTxLOL SquelchOnTxLOS Squelch R/W R/W Function Rev. 0.86 Si5040 FIFOAutoReset FIFOReset R/W R/W R/W 83 ...
Page 84
... Si5040 Register 157. TxtpSel Bit D7 D6 Name tpChkInvert Type R/W Reset settings = 0000 0000 Bit Name 7 tpChkInvert Test Pattern Checker Data Invert normal operation invert data applied to test pattern checker. 6:4 tpChkSel[2:0] Test Pattern Checker Mode Select. 000 = pattern checker disabled. ...
Page 85
... TxtpArbGenPtn[7:0] Transmitter Test Pattern Generator User Defined Pattern. Note: Bit 0 in Register 159 is the LSB of the 64-bit user-defined pattern, and Bit 7 in Register 166 is the MSB. The transmit sequence is from LSB to MSB tpSyncMask R Function TxtpArbGenPtn[7:0] R/W Function Rev. 0.86 Si5040 tpTimeBase[1:0] R/W R ...
Page 86
... Si5040 Register 160. TxtpArbGenPtn Bit D15 D14 Name Type Reset settings = 1010 1010 Bit Name 7:0 TxtpArbGenPtn[15:8] Transmitter Test Pattern Generator User Defined Pattern. Note: Bit 0 in Register 159 is the LSB of the 64-bit user-defined pattern, and Bit 7 in Register Register 161. TxtpArbGenPtn ...
Page 87
... TxtpArbGenPtn[47:40] R/W Function Register 166 is the MSB. The transmit sequence is from LSB to MSB. D53 D52 D51 TxtpArbGenPtn[55:48] R/W Function Register 166 is the MSB. The transmit sequence is from LSB to MSB. Rev. 0.86 Si5040 D34 D33 D32 D42 D41 D40 D50 D49 D48 87 ...
Page 88
... Si5040 Register 166. TxtpArbGenPtn Bit D63 D62 Name Type Reset settings = 1010 1010 Bit Name 7:0 TxtpArbGenPtn[63:56] Transmitter Test Pattern Generator User Defined Pattern. Note: Bit 0 in Register 159 is the LSB of the 64-bit user-defined pattern, and Bit 7 in Register 167. TxtpArbChkPtn ...
Page 89
... TxtpArbChkPtn[31:24] R/W Function in Register 174 is the MSB. The receive sequence is from LSB to MSB. D37 D36 D35 TxtpArbChkPtn[39:32] R/W Function in Register 174 is the MSB. The receive sequence is from LSB to MSB. Rev. 0.86 Si5040 D18 D17 D16 D26 D25 D24 D34 D33 D32 89 ...
Page 90
... Si5040 Register 172. TxtpArbChkPtn Bit D47 D46 Name Type Reset settings = 1010 1010 Bit Name 7:0 TxtpArbChkPtn[47:40] Transmitter Test Pattern Checker User Defined Pattern. Note: Bit 0 in Register 167 is the LSB of the received 64-bit user-defined pattern, and Bit 7 Register 173. TxtpArbChkPtn ...
Page 91
... When using a defined timebase, this register holds the error count from the last com- pleted timebase. In the continuous timebase setting, the register holds the current running error count. Reading the least significant byte LSB latches the upper bytes TxtpTargetErr[7:0] R/W Function 7 (decimal) 15 (decimal TxtpChkErrCnt[7:0] R Function Rev. 0.86 Si5040 ...
Page 92
... Si5040 Register 177. TxtpChkErrCnt (40-bit Register) Bit D15 D14 Name Type Reset settings = undefined Bit Name 7:0 TxtpChkErrCnt[15:8] Transmitter Test Pattern Checker Error Count. When using a defined timebase, this register holds the error count from the last com- pleted timebase. In the continuous timebase setting, the register holds the current running error count ...
Page 93
... TxtpChkErrCnt. Mantissa = bits [7:4] Exponent = bits [3:0] Error count = (Mantissa/16 0000 0000 = 0 (decimal) 0101 0111 = (5/16 1111 1111 = (15/16 D37 D36 D35 TxtpChkErrCnt[39:32] R Function 0000000000 = 0 (decimal) 40 FFFFFFFFFF = 2 – 1 (decimal TxtpChkErr[7:0] R Function Exponent 7 (decimal) 15 (decimal) Rev. 0.86 Si5040 D34 D33 D32 ...
Page 94
... Si5040 Register 184. OutputLevel Bit D7 D6 Name HsPowerCtl[1:0] Type R/W Reset settings = 1111 0101 Bit Name 7:6 Reserved Do not change; must only write 11 to these bits. 5:3 Reserved These bits are not user defined, and writes to these bits are ignored. 2:0 outLevel[2:0] Output Level ...
Page 95
... TX Loop Filter Setting for Acquisition. TX Loop filter override setting to be used during acquisiton. Set to 001 1000b when Tx LOL is asserted and to 000 0000 when Tx LOL is deasserted. Note that any read back may not return the last written value Reserved Function TxLoopFAcq[6:0] R/W Function Rev. 0.86 Si5040 R ...
Page 96
... CDRs. The use of a refer- ence clock is optional. If the jitter performance of the external reference clock is acceptable, the Si5040 can be operated in CMU mode. In this mode, the CMU derives the line-rate clock by multiplying the clock frequency applied to the REFCLK inputs. If the REFCLK input is synchronous, the CMU multiplies the frequency by 64 ...
Page 97
... Table 13. Si5040 Pin Descriptions (Continued) Pin Name Type* 2 RX_LOL DO 3 RX_LOS DO 22,21 TD+ AI Differential CML Transmitter Data Input. TD– 30,29 TXDOUT+ AO Differential CML Transmitter Data Output. TXDOUT– 24 SCK DIO Open Drain 9 SPSEL *Note: TYPE Power Analog Input Analog Output Digital Input Digital Output; DIO = Digital Input/Output ...
Page 98
... Si5040 Table 13. Si5040 Pin Descriptions (Continued) Pin Name Type GND P 17, 20, 23, 28, 31 Paddle GND P 12, 15, VDD P 27,32 4 VDDIO *Note: TYPE Power Analog Input Analog Output Digital Input Digital Output; DIO = Digital Input/Output. 98 Level Power and Ground GND Supply Ground. Connect to system GND. Ensure a very low impedance path for optimal performance ...
Page 99
... Ordering Guide Part Number Si5040-X-GM Notes: 1. “X” denotes product revision. 2. Add an “R” at the end of the device number to denote the tape and reel option; 2500 quantity per reel. Package Lead-Free 32-lead LGA Yes Rev. 0.86 Si5040 Temperature – °C 99 ...
Page 100
... Si5040 16. Package Outline: Si5040 Figure 25 illustrates the package details for the Si5040. Table 14 lists the values for the dimensions shown in the illustration. Figure 25. 32-Pin Land Grid Array Package (LGA) Table 14. Package Diagram Dimensions Dimension aaa bbb ccc ddd eee Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. ...
Page 101
... Recommended VDD Power Supply Filtering Because of the internal bypass capacitance and voltage regulators, the external supply bypass requirements for the Si5040 are minimal. 1 µF .01 µF Note: 1. Place a .01 µF cap very close to each VDD pin (12, 15, 27, 32) and place a single 0.1 µF cap close to the Si5040 ...
Page 102
... Si5040 OCUMENT HANGE IST Revision 0.2 to Revision 0.3 Pin assignment changes Block diagram changes Added package information V power supply recommendation DD Revision 0.3 to Revision 0.4 Added typical application schematic. Updated functional and detailed block diagrams. ...
Page 103
... Updated Section "12. Programmable Power Down Options." Added register summary and definitions in Section 13 for Registers 77, 98, 106-107, 205, and 226. Removed Section “18. Recommended Crystal Resonators” on page 94. Max power/current now specified for Mode 0 instead of Mode 3. Rev. 0.86 Si5040 103 ...
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... Si5040 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...