SI5040-D-GM Silicon Laboratories Inc, SI5040-D-GM Datasheet - Page 74

• Manufacturer Part Number: SI5040-D-GM
• Description: IC TXRX XFP 10GBPS 32LGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5040-D-GM

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si5040
Register 133. TxintStatus (Sticky Bits)
Reset settings = 0000 0000
74
Bit
7
6
5
4
3
2
1
0
Name
Type
Bit
tpErrAlarm
tpSyncLos
sqmAlarm
Reserved
refLOS
Name
fifoErr
LOS
LOL
D7
R
Read returns zero.
Reference Clock LOS Interrupt.
A latched version of the refLOS alarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
Loss of Signal Interrupt.
A latched version of the LOS alarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
Loss of Lock Interrupt.
A latched version of the LOL alarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
Transmitter FIFO Error Interrupt.
A latched version of the fifoErr alarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
Test Pattern Generator/Checker Alarm Interrupt.
A latched version of the tpErrAlarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
Test Pattern Checker Loss of Sync Interrupt.
A latched version of the tpSyncLos alarm status bit. An interrupt is generated if interrupts
are enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit.
The interrupt may be cleared by writing a zero to this bit position or by disabling inter-
rupts.
Signal Quality Monitor Alarm Interrupt.
A latched version of the sqmAlarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
refLOS
R/W
D6
LOS
R/W
D5
Rev. 0.86
LOL
R/W
D4
Function
fifoErr
R/W
D3
tpErrAlarm tpSyncLos
R/W
D2
R/W
D1
sqmAlarm
R/W
D0