SI5040-D-GM Silicon Laboratories Inc, SI5040-D-GM Datasheet - Page 77

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SI5040-D-GM

Manufacturer Part Number
SI5040-D-GM
Description
IC TXRX XFP 10GBPS 32LGA
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of SI5040-D-GM

Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Register 136. TxCalConfig
Reset settings = 0000 0000
Bit
7:4
2:1
3
0
Name
Type
Bit
VCOCAL[1:0]
hardRecal
Reserved
swReset
Name
D7
R
Read returns zero.
Force Recalibrations.
0 = Normal operation
1 = Initiate all calibrations of internal circuits and do not reset all Tx registers. Bit is
cleared upon completion of calibrations.
Transmit VCO Calibration Modes.
00 = (Default) Automatic detection of the reference clock is enabled. If the reference
clock is present, it will be used to center the internal VCO pull range at the beginning of
the lock acquisition process. Otherwise, the entire VCO frequency range will be swept.
01 = Enable referenceless operation. The entire VCO frequency range will be swept dur-
ing the CDR lock acquisition process regardless of the presence of the reference clock.
10 = Enable reference operation. The internal VCO pull range will be centered with the
reference clock frequency.
11 = Invalid mode. Note that transmit LOL will always be on.
Note: VCOCAL[1:0] must be set to reference(10b) or auto mode (00b) when part is configured to
Software Reset.
0 = Normal operation.
1 = Reset. Bit is cleared upon completion of reset.
D6
R
be in Lineside loopback mode.
D5
R
Rev. 0.86
D4
R
hardRecal
R/W
Function
D3
R/W
D2
VCOCAL[1:0]
R/W
D1
Si5040
swReset
R/W
D0
77

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