SI5040-D-GM Silicon Laboratories Inc, SI5040-D-GM Datasheet - Page 25

• Manufacturer Part Number: SI5040-D-GM
• Description: IC TXRX XFP 10GBPS 32LGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5040-D-GM

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.9. Receiver Phase Adjust
The Si5040 receiver supports programmable sample
phase adjust. The sampling point may be advanced or
delayed in time by adjusting the value loaded into the
RxPhaseAdjust register (Register 24). The range of
adjustment is ±12 ps.
5.10. Receive Clock Multiplier Unit
The Si5040 receiver incorporates a DSPLL
clock multiplier unit (CMU) that attenuates the jitter on
data recovered from the line interface. This makes it
much
requirements for 10 Gbit SONET, Ethernet, and Fibre
Channel applications. The CMU is rate-adaptable
across the entire range of device operation. Note that
when the ltr bit or ltrOnLOS bit in Register 7 is set to 1,
the receive CMU is locked to the reference clock.
The receiver CMU supports 380 kHz bandwidth
(cmuBandwidth[3:0] at Register 6 = 0100).
00: Disabled (Default)
01: Based on consecutive number of 1s
01: Based on consecutive number of 0s
01: Based on either consecutive number of 1s or 0s
(Bit 2:1, Register 138)
easier
dLosEn[1:0]
TxdLosAssertThresh[7:0] (Bit 7:0, Register 145)
TxSqmDeassertThresh[5:0] (Bit 5:0, Register 155)
TxdLosClearThresh (Bit 7:0, Register 146)
to
(Bit 5:0, Register 153)
1
TxSqmThresh[5:0] (Bit 7:2, Register 154)
TxSqmValue[5:0]
significantly
EN
EN
Tx Recovered Clock
Monitor
Quality
Monitor
Signal
DLOS
Reference Clock
Figure 16. Tx LOS and LOL Block Diagram
exceed
(Bit 0, Register 137)
sqmLosEn
(Bit 3, Register 138, Default= 0)
sqmAlarm
the
®
-based
jitter
Rev. 0.86
Frequency
Monitor
Offset
(Bit 4, Register 139)
5.11. Recommended Pre-Emphasis on the
Even though the RD signal rise/fall time is very fast,
some users may wish to add high-frequency boost to
the RD signal. This is done with an external RC network
to reduce low-frequency energy, effectively boosting the
high frequencies. To compensate for loss in the circuit
and maintain proper signal size and eye opening at the
XFI connector, the RD amplitude will have to increase to
700 or 800 mV. Register 56 controls the RD signal
amplitude. The resistors and capacitors can be generic
low-cost components, and the circuit should be located
very close to the Si5040 RD± pins. This circuit is
recommended for all XFP applications.
(Bit 2, Register 139)
(Bit 2, Register 135)
sqmLOS
dLOS
RD Signal
SqmLol
FreqLol
lolMode
1 (Default)
0
Select
(Bit 3, Register 135, Default= 0)
useLolMod
(Bit 5, Register 137 or
Bit 0, Register 139)
LOS
(Bit 4, Register 137)
Si5040
LOL
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