SI5040-D-GM Silicon Laboratories Inc, SI5040-D-GM Datasheet - Page 48

• Manufacturer Part Number: SI5040-D-GM
• Description: IC TXRX XFP 10GBPS 32LGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5040-D-GM

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si5040
Register 9. RxAlarmStatus
Reset settings = 0000 0000
48
Bit
7
6
5
4
3
2
1
0
Name
Type
Bit
tpErrAlarm
tpSyncLos
sqmAlarm
Reserved
refLOS
Name
fifoErr
LOS
LOL
D7
R
Read returns zero.
Reference Clock LOS Alarm.
Loss of signal on the reference clock input, based on a coarse deviation in frequency.
Loss of Signal Alarm.
Loss of signal on the receiver input.
Note: This bit is the logical OR of the Analog LOS (aLOS), Digital LOS (dLOS) and Signal Quality
Loss of Lock Alarm.
The receiver PLL has lost lock with the input signal. Reflects the state of the RX_LOL pin
(pin 2).
Receiver FIFO Error Alarm.
The receiver FIFO has overflowed or underflowed. If FIFOAutoReset is active
(Reg28[1] = 1), this bit is automatically cleared when a FIFO over/under flow has
occurred.
Test Pattern Generator/Checker Alarm.
The receiver test pattern checker has reached the predetermined error count set in Reg-
ister 47.
Test Pattern Checker Loss-of-Sync Alarm.
The receiver test pattern checker has lost sync with the pattern. When the test pattern
checker is disabled, this bit is automatically set to 0. When the test pattern checker is
enabled, an “I” in this location means the test pattern checker has lost synchronization
between the expected pattern and the received pattern.
Signal Quality Monitor Alarm.
The internal signal quality monitor value has met the predetermined threshold value.
refLOS
D6
R
Monitor LOS (sqmLOS) alarms, which can be enabled individually by programming
Register 10.
LOS
D5
R
Rev. 0.86
LOL
D4
R
Function
fifoErr
D3
R
tpErrAlarm tpSyncLos sqmAlarm
D2
R
D1
R
D0
R