SI5040-D-GM Silicon Laboratories Inc, SI5040-D-GM Datasheet - Page 57

• Manufacturer Part Number: SI5040-D-GM
• Description: IC TXRX XFP 10GBPS 32LGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5040-D-GM

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register 28. RxdPathConfig
Reset settings = 0000 0010
Bit
7
6
5
4
3
2
1
0
Name
Type
Bit
SquelchOnRxLOS Data Squelch on Receive Loss of Signal.
SquelchOnRxLOL Data Squelch on Receive Loss of Lock.
FIFOAutoReset
FIFOReset
clkOnLOS
Reserved
Squelch
dinvert
Name
D7
R
dinvert
R/W
D6
Read returns zero.
Data Invert.
0 = Normal operation.
1 = RD+ and RD– outputs (pins 19, 18) inverted.
Clock Output on Receive Loss of Signal.
0 = Normal operation.
1 = 622 MHz clock output on RD+ and RD– on receiver LOS condition.
0 = Normal operation.
1 = Squelch RD+ and RD– outputs (pins 19, 18) on receiver Loss of Lock condition.
0 = Normal operation.
1 = Squelch RD+ and RD– outputs (pins 19, 18) on receiver Loss of Signal condition.
Data Squelch.
0 = Normal operation.
1 = Squelch RD+ and RD– outputs (pins 19, 18).
FIFO Auto Reset.
0 = No reset of receive FIFO on FIFO error.
1 = Automatically reset receive FIFO on FIFO underflow or overflow and clear fifoerr
bit in RXintMask register (Reg4[1]). FIFO pointer is reset to center value and FIFO is
cleared.
FIFO Reset.
0 = Normal operation.
1 = Reset receive FIFO. FIFO pointer is reset to center value and FIFO is cleared.
clkOnLOS SquelchOn
R/W
D5
RxLOL
R/W
Rev. 0.86
D4
SquelchOn
RxLOS
R/W
D3
Function
Squelch
R/W
D2
FIFOAuto
Reset
R/W
D1
Si5040
FIFOReset
R/W
D0
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