SI5040-D-GM Silicon Laboratories Inc, SI5040-D-GM Datasheet - Page 102

• Manufacturer Part Number: SI5040-D-GM
• Description: IC TXRX XFP 10GBPS 32LGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5040-D-GM

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si5040
D
Revision 0.2 to Revision 0.3
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Revision 0.3 to Revision 0.4
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Revision 0.4 to Revision 0.5
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102
OCUMENT
Pin assignment changes
Block diagram changes
Added package information
V
Added typical application schematic.
Updated functional and detailed block diagrams.
Revised CDR acquisition time when in reference
clock mode.
Noted LVTTL DC parameters not characterized for
VDDIO= 1.8 V.
Specified DJ and TJ measuring bandwidth for RD
output.
RD max peak amplitude changed from 400 mV to
385 mV.
TXDOUT max peak amplitude changed from
450 mV to 525 mV.
Updated TD jitter tolerance curve.
Noted ALOS band limited to 2 GHz.
Added LOS and LOL consequent actions.
Added descriptions for receive CMU.
Noted PRBS pattern inversion possibility.
Updated Register 2 and 134 default values.
Clarified VCOCAL[1:0] in Registers 8 and 136.
Clarified dLosEN in Register 10.
Clarified Registers 13, 22, 45, and 175.
Added a note to recalibrate after bandwidth change
in Register 134.
Clarified CMU bandwidth setting in Register 134.
Clarified pin descriptions.
Updated power supply filtering recommendation.
Updated power consumption numbers.
Updated detailed block diagram.
Increased max ambient temperature from 85 °C to
95 °C.
Updated min ppm drift for the PLL to go out of lock
from 1000 ppm to 800 ppm.
Updated jitter generation specification at TXDOUT.
Updated application schematic.
Updated dLos set and clear flowcharts.
Updated Rx LOS and LOL block diagram and added
one for Tx side.
DD
power supply recommendation
C
HANGE
L
IST
Rev. 0.86
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Revision 0.5 to Revision 0.8
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Added descriptions and registers for Rx Equalizer.
Added I2C address explanations.
Updated interrupt function descriptions and added
an Interrupt Tree diagram.
Added descriptions for Programmable Power Down
Options.
Updated register summary table and register
description sections.
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Updated power supply filtering recommendation.
Added crystal resonators recommendation.
Added Register 56, bits 7:6, and Register 184, bits
7:6 for Rx and Tx 11.4 Gbps support.
Added Register 56, bits 2:0 for RD output level
control.
Changed phase adjustment range to ±12 ps instead
of ±30 ps.
Added 100 kHz and 300 kHz Rx jitter transfer
bandwidth options.
Updated final specification numbers for TBD items.
Updated register name in Register 16.
Changed aLosThresh[1:0] to aLosThresh[9:8] in
Register 13.
Jitter Tolerance measurement frequency changed
from 400 MHz to 80 MHz.
Corrected typos in the jitter transfer bandwidth
specification in Tables 4 and 5.
Corrected typos in Table 6, “CMU Timing Modes,” on
page 12.
Updated crystal recommendation list.
Removed I2C fall time spec in Table 8.
Updated Constant Duty Cycle Control range to show
adjustment range of 26% to 74% in Registers 21 and
22.
Updated default values for all registers.
Made RxdLosNoPulseThresh[3:0] and
RxdLosClearWindow[3:0] at Register 19 Reserved
register fields with default = 0.
Corrected equations for RxdLosAssertThresh[7:0] at
Register 17, RxdLosClearThresh[7:0] at Register 18,
TxdLosAssertThresh[7:0] at Register 145 and
TxdLosClearThresh[7:0] at Register 146.
Updated lolMode and useLolMode in Register 7 and
135.
Eliminated 63-bit user pattern support.
Eliminated Tx and Rx test clock support on Pin 2 and
Pin 3.