SI5040-D-GM Silicon Laboratories Inc, SI5040-D-GM Datasheet - Page 23

• Manufacturer Part Number: SI5040-D-GM
• Description: IC TXRX XFP 10GBPS 32LGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5040-D-GM

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

receiver may be running at a different rate than the
transmitter, the user is given the option of disabling the
reference clock on the receiver.
The RxrefclkEn bit in the RxConfig register (Register 7)
controls this function. The receiver can be locked to the
reference clock under the following programmable
conditions: (RxConfig, Register 7)
1. Set LTR (bit 1).
2. Set LTR on receive loss-of-signal (LOS) (bit 5).
Note: If it is desired to allow the CDR to acquire lock to the
5.8. Receiver Loss of Lock (LOL)
Receiver LOL functions differently depending on
whether the receiver is operating in reference or
referenceless mode. By default (uselolmode Register 7,
Bit 3 = 0), SQM-based LOL is used in referenceless
mode, and Frequency-based LOL is used in reference
mode. In reference mode however, either SQM or
Frequency LOL can be used by setting Register 7, Bits
2 and 3 to the appropriate values.
5.8.1. SQM LOL
When the VCO is configured to calibrate without a
reference clock (VCOCAL[1:0] = 01 binary), the default
values of register 7[3:2] will cause the LOL method to
be SQMLOL. The SQMLOL method compares an
internal jitter measure to the sqmLOLThresh (see below
on how to set this threshold). When the internal jitter
measure is greater than the sqmLOLThresh, RXLOL is
asserted. When RxLOL is asserted the 5040 Rx side
will automatically start to try to acquire lock again across
an input data range of 9.9–11.4 Gbps. RxLOL is
deasserted when the jitter measure is less than the
sqmLOLThresh. The sqmLOLThreshold must be set
using registers 106, 107, 108, and 109 in the following
order:
1. Write register 107 = A0h.
2. Write register 108 = 3Fh.
3. Write register 109 = B9h.
4. Write register 106 = 04h.
5. Write register 106 = 84h.
These are indexed address registers. Register 106
contains the sqmLOLThresh register address and 107-
109 contain the data to be written to it. Register 106
must be written twice. The first write of 04h sets the
address, and 84h applies the value in 107-109 into the
incoming data while LTR at Register 7, Bit 1 is set to 1
(Lock to Reference clock enabled), set CDRLTDATA at
Register 7, Bit 4 to 1 (default). If it is desired to sample
the incoming data with a programmable phase and
slice level while LTR is set to 1, set sliceEn[2:0] at Reg-
ister 20 to 000 binary (auto slice disabled).
Rev. 0.86
sqmLOLThresh registers. The above values are
recommended for all applications.
Using sqmLOLThresh values other than the default or
the one given above can cause unexpected problems,
such as false lock, and are not recommended.
5.8.1.1. Dynamic Register Control
The dynamic control of RxLoopFAcq (Register 98) is
required to ensure the locking performance of the CDR.
It is required for all applications that RxLoopFAcq be set
to 98h when Rx LOL is asserted and to 00h when Rx
LOL is deasserted. Only the default value and the value
given above are supported for writes to Register 98.
Any read back of this register will not necessarily return
the value written.
In addition, for proper LOL performance, RxPDGainAcq
(Register 77) must be written once to 0Dh after power is
applied or a SW reset is implemented.
5.8.2. Frequency LOL
The Si5040 supports the use of a ~622 MHz or
~155 MHz (/64 or /16) reference clock. The reference
clock frequency is selected in the ChipConfig1 register
(Register 2). When FREQLOL is set (Register
7[3:2] = 10b) and rxrefcken is true (reg7[0]), LOL is
asserted if the recovered clock frequency deviates from
the reference clock frequency by ±1000 ppm. LOL is de-
asserted if the recovered clock is within ±200 ppm of the
reference clock frequency. Refer to Figure 14 for CDR
and VCO behaviors upon declaring LOL. Note that
when using Frequency LOL, Registers 77 and 98 do not
need to be modified from their default values.
5.8.3. Acquisition Time Enhancement
The acquisition lock time for a signal applied at RXDIN
can be reduced to less than 15 ms by the following
register writes:
1. Write register 86 = 0011 0000 = 30h.
2. Write register 67 = 0100 0001 = 41h.
3. Write register 68 = 0000 0011 = 03h.
5.8.4. LOL Interrupt
LOL may be configured to generate an interrupt. The
status of the LOL interrupt bit can be read from the
RxintStatus register (Register 5). The status of LOL may
also be read from the RxAlarmStatus register (Register
9). LOL may also be asserted upon activation of LOS
(see "5.4. Receiver Loss of Signal Alarm (LOS)" on
page 19 and Figure 15 on page 24). Receive data (RD)
may be squelched on LOL. This option is configured in
the RxdPathConfig register (Register 28).
Si5040
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