SI5040-D-GM Silicon Laboratories Inc, SI5040-D-GM Datasheet - Page 30

• Manufacturer Part Number: SI5040-D-GM
• Description: IC TXRX XFP 10GBPS 32LGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5040-D-GM

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si5040
7. Loopback Modes
The Si5040 supports XFI Loopback, Lineside Loopback,
and Looptime modes.
7.1. XFI Loopback
The Si5040 is configured in the XFI Loopback mode by
writing to the ChipConfig1 register (Register 2). The
Si5040 is configured in the XFI Loopback mode by
writing to the ChipConfig1 register (Register 2). Data on
the TD input is retimed and output on the RD output.
The clock recovered from the XFI data (TD) is used as
the timing source for the RD output. For this reason, RX
VCOCAL (Register 8, Bit [2:1]) must be set to reference
or auto mode. If the data from the transmitter is not
required at the TXDOUT output pins, it may be disabled
by writing to the transmitter Squelch bit in the dPath
register (Register 156, bit 2). Data on the TD input is
retimed and output on the RD output. The clock
recovered from the XFI data (TD) is used as the timing
source for the RD output.
7.2. Lineside Loopback
The Si5040 is configured in the Lineside Loopback
mode by writing to the ChipConfig1 register (Register
2). Data received on the receiver input (RXDIN) is
output on the transmitter (TXDOUT) output. Since in
this mode the clock recovered from the receiver input is
used as the timing source for the transmit CMU, TX
VCOCAL (Register 136, Bit [2:1]) must be in reference
or auto mode. If the data from the receiver is not
required at the XFI interface, it may be disabled by
writing to the receiver Squelch bit in the dPath register
(Register 28, bit 2).
8. Looptime Mode
The Si5040 supports looptime mode for applications in
which it is desirable to time the transmitter off the
receiver clock. Data received at the XFI interface (TD) is
retimed using the clock recovered from the receiver
(RXDIN). As a result of the transmit CMU jitter
attenuation feature in the Si5040, with the appropriate
setting of the CMU bandwidth (set in Register 134), the
jitter on the recovered clock is significantly attenuated
so that the data on the transmit output will be compliant
with the datacom and telecom standards supported by
the Si5040. A FIFO within the data path accommodates
any jitter differences between the serial data and the
CMU line-rate clock. Looptime mode is enabled by
writing to the TxCmuConfig register (Register 134).
30
Rev. 0.86
9. Pattern Generation and Checking
The Si5040 includes a programmable pattern generator
and checker function in both the receiver and
transmitter signal paths. The Si5040 can generate and
check PRBS7, PRBS31, or a 64-bit, user-defined
pattern programmed in the tpSel register (receiver
Register 29, transmitter Register 157).
Notes:
The user-defined patterns are programmed in the
tpArbGenPtn and tpArbChkPtn registers (receiver
Registers 31–38 and transmitter Registers 159–166).
The time period or number of bits over which the
checker should look for errors is defined in the
tpTimeBase bits located in the tpChkConfig register
(receiver Register 30, transmitter Register 158). The
time base can be programmed to be infinite (always
looking for errors) or set to one of three defined values.
Changing to another time base will reset the error
counter.
The pattern checker offers a Loss-of-Sync indicator
along with a 40-bit error count register and an 8-bit error
count register in floating point notation. When the
checker
expected and the received pattern, the tpSyncLos
register (receiver Register 9, transmitter Register 137)
is deasserted. Note that as soon as the checker is
synchronized, the error count register is reset to 0, and
error counting begins. As soon as the checker loses
synchronization in the middle of a measuring window
defined by the tpTimeBase register, the error count
register is loaded with all 1s, indicating the maximum
error count. In order to differentiate between a Loss-of-
Sync event and a bit error event, the user should
monitor both the tpSyncLos register and the error count
register described below.
1. When PRBS7 or PRBS31 is selected for the pattern
2. The pattern checker will report no error if the input
generator or checker, the pattern can either be inverted
or non-inverted by programming the tpGenInvert and
tpChkInvert bits in the pgSel register (receiver Register
29, transmitter Register 157). Per Section 5.8 in O.150,
PRBS31 is specified as an inverted pattern. The
pattern generators default to generating an inverted
PRBS31 to comply with 0.150. However, the pattern
generators and checkers have the option to invert the
pattern.
sequence is an all 0s pattern. However, a loss-of-lock
or loss-of-signal indicator will assert in these
conditions.
achieves
synchronization
between
the