SI5040-D-GM Silicon Laboratories Inc, SI5040-D-GM Datasheet - Page 28

• Manufacturer Part Number: SI5040-D-GM
• Description: IC TXRX XFP 10GBPS 32LGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5040-D-GM

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si5040
6.4.2. Frequency LOL
The Si5040 supports the use of a ~622 MHz or
~155 MHz
FREQLOL is set (Register 135[3:2] = 10b), LOL is
asserted if the recovered clock frequency deviates from
the reference clock frequency by ±1000 ppm. LOL is de-
asserted if the recovered clock is within ±200 ppm of the
reference
frequency is selected in the ChipConfig1 register
(Register 2). Refer to Figure 14 for CDR and VCO
behaviors upon declaring LOL. Note that when using
Frequency LOL, Registers 205 and 226 do not need to
be modified from their default values.
6.4.3. Acquisition Time Enhancement
The acquisition time for a signal applied at TD can be
reduced to less than 10 ms by the following register
writes:



6.4.4. LOL Interrupt
LOL may be configured to generate an interrupt. The
status of the LOL interrupt bit can be read from the
TxintStatus register (Register 133). The status of LOL
may also be read from the TxAlarmStatus register
(Register 137). Transmitter data (TXDOUT) may be
squelched on LOL. This option is configured in the
TxdPathConfig register (Register 156).
6.5. Transmitter Phase Adjust
The Si5040 transmitter supports manual sample phase
adjust. The sampling point may be advanced or delayed
in time by adjusting the value loaded into the
PhaseAdjust register (Register 152). The range of
adjustment is >±12 ps. Note that the transfer function
from the register value to the phase adjust time is highly
variable; therefore, we only guarantee that the largest or
smallest register value will achieve better than +12 ps or
–12 ps, respectively.
6.6. Transmit Clock Multiplier Unit
The Si5040 transmitter incorporates a DSPLL
clock multiplier unit (CMU) that attenuates the jitter on
the data recovered from the XFI interface. This makes it
much
requirements for 10 Gbit SONET, Ethernet, and
FibreChannel applications. The CMU is rate-adaptable
across the entire range of device operation. Selectable
CMU bandwidths support adjustment of the degree of
jitter filtering required for a given application.
28
Register 195 = 40h
Register 196 = 07h
Register 214 = 38h
easier
clock
(/64
to
or
frequency.
significantly
/16)
reference
The
exceed
reference
clock.
the
®
-based
When
clock
jitter
Rev. 0.86
6.7. Timing Modes Of Operation
For maximum flexibility, the Si5040 supports three CMU
timing modes that make it suitable for XFP modules
targeted at both datacom and telecom applications. The
modes of operation determine how the transmit CMU is
configured. Timing modes are set in the TxCmuConfig
register (Register 134).
6.7.1. Referenceless Mode (Mode 0)
In the referenceless mode of operation, timing
information is recovered from the XFI data and used as
the timing source for the transmit CMU (Figure 18). The
mode is set in TxCmuConfig (Register 134). This mode
should be chosen when a synchronous reference clock
is not available or if the jitter on the recovered XFI data
is less than that on the available synchronous reference
clock.
Optionally, an asynchronous reference clock at a
frequency of 1/64 of the baud rate (as defined in the
XFP specification) may be applied for VCO centering
purposes and to generate receive LOL and transmit
LOL. However, a reference clock is not necessary to
generate these signals. Referenceless mode is the
default mode after power-on.
6.7.2. Synchronous Reference Clock Mode (Mode 1)
If an external synchronous reference clock with jitter
characteristics of higher quality than those of the
recovered XFI clock is available, the device may be
operated in Synchronous Reference Clock Mode
(Figure 19). The mode is set in TxCmuConfig (Register
134). In this mode, the transmit CMU derives the line-
rate clock by multiplying the clock frequency applied to
the REFCLK inputs by 64. This mode is equivalent to
the
described in the XFP specification (see XFP MSA Rev.
4.0 Section 3.9.1). It is not necessary to meet the phase
noise characteristics defined for the synchronous
reference clock in the XFP specification since the
Si5040 transmit CMU attenuates jitter on the reference
clock.
"Optional
Synchronous
CMU
Clock"
mode